74AC244 • 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs
November 1988
Revised March 2005
74AC244 • 74ACT244
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The AC/ACT244 is an octal buffer and line driver designed
to be employed as a memory address driver, clock driver
and bus-oriented transmitter/receiver which provides
improved PC board density.
Features
s
I
CC
and I
OZ
reduced by 50%
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
ACT244 has TTL-compatible inputs
Ordering Code:
Order Number
74AC244SC
74AC244SCX_NL
(Note 1)
74AC244SJ
74AC244MTC
74AC244MTCX_NL
(Note 1)
74AC244PC
74ACT244SC
74ACT244SCX_NL
(Note 1)
74ACT244SJ
74ACT244MSA
74ACT244MTC
74ACT244MTCX_NL
(Note 1)
74ACT244PC
Package
Number
M20B
M20B
M20D
MTC20
MTC20
N20A
M20B
M20B
M20D
MSA20
MTC20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.
FACT
¥
is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009943
www.fairchildsemi.com
74AC244 • 74ACT244
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
AC
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
'
V/
'
t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (
'
V/
'
t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 5)
I
OZ
Maximum Input
Leakage Current
Maximum
3-STATE
Current
I
OLD
I
OHD
I
CC
(Note 5)
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
4.0
50
75
mA
mA
5.5
V
I
(OE)
V
IL
, V
IH
5.5
0.002
0.001
0.001
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
25
q
C
T
A
55
q
C to
125
q
C T
A
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.4
3.7
4.7
0.1
0.1
0.1
0.50
0.50
0.50
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
Units
Conditions
V
OUT
0.1V
V
or V
CC
0.1V
V
OUT
0.1V
V
or V
CC
0.1V
V
I
OUT
I
OH
50
P
A
12 mA
24 mA
24 mA (Note 3)
50
P
A
12 mA
24 mA
24 mA (Note 3)
V
CC
, GND
V
I
OH
I
OH
V
I
OUT
I
OL
V
I
OL
I
OL
V
I
r
0.1
r
1.0
r
1.0
P
A
r
0.25
r
5.0
r
2.5
P
A
V
I
V
O
V
CC
, V
GND
V
CC
, GND
1.65V Max
3.85V Min
V
CC
V
OLD
V
OHD
V
IN
or GND
50
80.0
75
40.0
P
A
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3
www.fairchildsemi.com
Test/Measurement
京公网安备 11010802033920号
EEWORLD
