®
74ACT163
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
=200 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
= 25
o
C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN), V
IL
= 0.8V (MAX)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 163
IMPROVED LATCH-UP IMMUNITY
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT163B
74ACT163M
Enable Input (LOAD), Count Enable Input (PE)
and Count Enable Carry Input (TE), determine
the mode of operation as shown in the Truth
Table. A LOW signal on CLEAR overrides
counting and parallel loading and allows all
output to go LOW on the next rising edge of
CLOCK. A LOW signal on LOAD overrides
counting and allows information on Parallel Data
Qn inputs to be loaded into the flip-flops on the
next rising edge of CLOCK. With LOAD and
CLEAR, PE and TE permit counting when both
are HIGH. Conversely, a LOW signal on either
PE and TE inhibits counting.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The ACT163 is a high-speed CMOS
SYNCRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
2
double-layer metal wiring C MOS technology. It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
Schottky TTL. It is a 4 bit binary counter with
Synchronous Clear.
The circuits have four fundamental modes of
operation, in order of preference: synchronous
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
PIN CONNECTION AND IEC LOGIC SYMBOLS
December 1998
1/11
74ACT163
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2
3, 4, 5, 6
7
10
9
14, 13, 12,
11
10
8
16
SYMBOL
CLEAR
CLOCK
A, B, C, D
NAME AND FUNCT ION
Master Reset
Clock Input (LOW-to-HIGH,
Edge- Triggered)
Data Inputs
ENABLE P Count Enable Input
ENABLE T Count Enable Carry Input
LOAD
QA to QD
Parallel Enable Input
Flip-Flop Outpus
ENABLE T Count Enable Carry Input
GND
V
CC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUT S
CLR
L
H
H
H
H
X
NOTE:
O UT PUT S
TE
X
X
L
X
H
X
CK
QA
L
A
QB
L
B
QC
L
C
QD
L
D
FUNCT ION
RESET TO ”0”
PRESET DATA
NO COUNT
NO COUNT
COUNT
NO COUNT
LD
X
L
H
H
H
X
PE
X
X
X
L
H
X
NO CHANGE
NO CHANGE
COUNT UP
NO CHANGE
X:Don’t Care
A,B, C,D: Logic level of data input
CARRY=TE
•
QA
•
QB
•
QC
•
QD
LOGIC DIAGRAMS
2/11
74ACT163
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
300
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
o
o
I
CC
or I
GND
DC V
CC
or Ground Current
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature:
Input Rise and Fall Time V
CC
= 4.5 to 5.5V (note 1)
Parameter
Value
4.5 to 5.5
0 to V
CC
0 to V
CC
-40 to +85
8
Unit
V
V
V
o
C
ns/V
1) V
IN
from 0.8 V to 2.0 V
DC SPECIFICATIONS
Symb ol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Low Level Output Voltage
4.5
5.5
4.5
5.5
I
I
I
CCT
I
CC
I
OLD
I
OHD
Input Leakage Current
Max I
CC
/Input
Quiescent Supply Current
Dynamic Output Current
(note 1, 2)
5.5
5.5
5.5
5.5
V
I (* )
=
V
IH
or
V
IL
V
O
= 0.1 V or
V
CC
- 0.1 V
V
O
= 0.1 V or
V
CC
- 0.1 V
V
I (* )
=
V
IH
or
V
IL
I
O
=-50
µA
I
O
=-50
µA
I
O
=-24 mA
I
O
=-24 mA
I
O
=50
µ
A
I
O
=50 mA
I
O
=24 mA
I
O
=24 mA
V
I
= V
CC
or GND
V
I
= V
CC
-2.1 V
V
I
= V
CC
or GND
V
OLD
= 1.65 V max
V
OHD
= 3.85 V min
0.6
4
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
2.0
2.0
T yp.
1.5
1.5
1.5
1.5
4.49
5.49
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1
1.5
40
75
-75
Max.
-40 to 85 C
Min.
2.0
2.0
0.8
0.8
Max.
o
Un it
V
V
V
V
µA
mA
µ
A
mA
mA
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
Ω.
(*) All outputs loaded.
4/11
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