74ACT825 8-Bit D-Type Flip-Flop
July 1988
Revised September 2000
74ACT825
8-Bit D-Type Flip-Flop
General Description
The ACT825 is an 8-bit buffered register. They have Clock
Enable and Clear features which are ideal for parity bus
interfacing in high performance microprogramming sys-
tems. Also included are multiple enables that allow multi-
use control of the interface. The ACT825 has noninverting
outputs.
Features
s
Outputs source/sink 24 mA
s
Inputs and outputs are on opposite sides
s
TTL compatible inputs
Ordering Code:
Order Number
74ACT825SC
74ACT825MTC
74ACT825SPC
Package Number
M24B
MTC24
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
O
0
–O
7
OE
1
, OE
2
, OE
3
EN
CLR
CP
Description
Data Inputs
Data Outputs
Output Enables
Clock Enable
Clear
Clock Input
FACT is a trademark of Fairchild Semiconductor.
© 2000 Fairchild Semiconductor Corporation
DS009895
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74ACT825
Functional Description
The ACT825 consists of eight D-type edge-triggered flip-
flops. These devices have 3-STATE outputs for bus sys-
tems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE
1
, OE
2
and OE
3
LOW, the contents of the flip-flops are available at the out-
puts. When one of OE
1
, OE
2
or OE
3
is HIGH, the outputs
go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops. The ACT825 has Clear (CLR) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
OE
H
H
H
L
H
L
H
H
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Internal
CP
Output
Function
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
High-Z
High-Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
CLR
X
X
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
X
X
X
D
n
L
H
X
X
X
X
L
H
L
H
Q
L
H
L
L
NC
NC
L
H
L
H
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACT825
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source or Sink Current
(I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
140
°
C
−
0.5V to 7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
+
0.5V
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input Leakage Current
Maximum
3-STATE Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
5.5
8.0
0.6
0.001
0.001
T
A
=
25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
±0.5
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
±5.0
1.5
75
−75
80
µA
µA
mA
mA
mA
µA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−0.1V
V
OUT
=
0.1V
or V
CC
−0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Units
Conditions
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
3
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74ACT825
AC Electrical Characteristics
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock
Frequency
Propagation Delay
CP to O
n
Propagation Delay
CP to O
n
Propagation Delay
CLR to O
n
Output Enable Time
OE to O
n
Output Enable Time
OE to O
n
Output Disable Time
OE to O
n
Output Disable Time
OE to O
n
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Min
120
1.5
2.0
2.5
1.5
2.0
1.5
1.5
Typ
158
5.5
5.5
8.0
6.0
6.5
6.5
6.0
9.5
9.5
13.5
10.5
11.0
11.0
10.5
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
109
1.5
1.5
2.0
1.5
1.5
1.5
1.5
10.5
10.5
15.5
11.5
12.0
12.0
11.5
Max
MHz
ns
ns
ns
ns
ns
ns
ns
Units
Parameter
(V)
(Note 4)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
Setup Time, HIGH or LOW
EN to CP
Hold Time, HIGH or LOW
EN to CP
CP Pulse Width
HIGH or LOW
t
W
t
REC
CLR Pulse Width, LOW
CLR to CP
Recovery Time
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Typ
0.5
0
0
0
2.5
3.0
1.5
2.5
2.5
2.0
1.0
4.5
5.5
3.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
2.5
2.5
2.5
1.0
5.5
5.5
4.0
ns
ns
ns
ns
ns
ns
ns
Units
(V)
(Note 5)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
44
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
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74ACT825
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
5
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