INTEGRATED CIRCUITS
DATA SHEET
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
Product specification
Supersedes data of 1999 May 31
File under Integrated Circuits, IC06
1999 Sep 24
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V;
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
•
Balanced propagation delays
•
Inputs accepts voltages higher than
V
CC
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Specified from
−40
to +85 and +125
°C.
DESCRIPTION
The 74AHC/AHCT132 are
high-speed Si-gate CMOS devices
and are pin compatible with Low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT132 contain four
2-input NAND gates which accept
standard input signals. They are
capable of transforming slowly
changing input signals into sharply
defined, jitter free output signals.
The gate switches at different points
for positive and negative-going
signals. The difference between the
positive voltage V
T+
and the negative
V
T−
is defined as the hysteresis
voltage V
H
.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC132D
74AHC132PW
74AHCT132D
74AHCT132PW
Note
FUNCTION TABLE
See note 1.
INPUTS
nA
L
L
H
H
74AHC132; 74AHCT132
OUTPUT
nB
L
H
L
H
nY
H
H
H
L
1. H = HIGH voltage level; L = LOW voltage level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
O
C
PD
PARAMETER
propagation delay
nA to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.3
3.0
4.0
11
AHCT
3.5
3.0
4.0
14
ns
pF
pF
pF
UNIT
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PACKAGES
NORTH AMERICA
PINS
74AHC132D
74AHC132PW DH
74AHCT132D
74AHCT132PW DH
14
14
14
14
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
1999 Sep 24
2
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74AHC132; 74AHCT132
handbook, halfpage
1
2
4
5
9
10
12
13
&
3
&
6
handbook, halfpage
A
Y
&
8
B
MNA409
&
11
MNA408
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one Schmitt trigger).
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
DC supply voltage
input voltage
output voltage
operating ambient temperature
range
see DC and AC
characteristics per
device
CONDITIONS
MIN.
2.0
0
0
−40
−40
TYP. MAX. MIN.
5.0
−
−
+25
+25
5.5
5.5
V
CC
+85
4.5
0
0
−40
TYP. MAX.
5.0
−
−
+25
+25
5.5
5.5
V
CC
+85
V
V
V
°C
74AHCT
UNIT
+125
−40
+125
°C
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70
°C
the value of P
D
derates linearly with 8 mW/K.
For TSSOP packages: above 60
°C
the value of P
D
derates linearly with 5.5 mW/K.
PARAMETER
DC voltage
input voltage range
DC input diode current
DC output diode current
DC V
CC
or GND current
storage temperature range
power dissipation per package
for temperature range:
−40
to +125
°C;
note 2
V
I
<
−0.5
V; note 1
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V; note 1
CONDITIONS
MIN. MAX. UNIT
−0.5
−0.5
−
−
−
−
−65
−
+7.0
+7.0
−20
±20
±25
±75
500
V
V
mA
mA
mA
mA
mW
DC output source or sink current
−0.5
V < V
O
< V
CC
+ 0.5 V
+150
°C
1999 Sep 24
4
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