Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger
actions
•
Inputs accepts voltages higher than
V
CC
•
Common 3-state output enable
input
•
I
CC
category: MSI
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Specified from
−40
to +85 and +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
DESCRIPTION
74AHC374;
74AHCT374
The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs.
TYPICAL
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
O
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
propagation delay;
CP to Q
n
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
3.5
50
3.0
4.0
10
AHCT
5.0
−
3.0
4.0
12
ns
MHz
pF
pF
pF
UNIT
1999 Sep 28
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FUNCTION TABLE
See note 1.
INPUTS
OPERATING MODES
OE
Load and read register
Load register and
disable outputs
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care;
Z = high-impedance OFF-state;
↑
= LOW-to-HIGH CP transition.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC374D
74AHC374PW
74AHCT374D
74AHCT374PW
PINNING
PIN
1
2, 5, 6, 9, 12, 15,
16 and 19
3, 4, 7, 8, 13, 14,
17 and 18
10
11
20
OE
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
SYMBOL
3-state flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
DC supply voltage
DESCRIPTION
3-state output enable input (active LOW)
PACKAGES
NORTH AMERICA
PINS
74AHC374D
74AHC374PW DH
74AHCT374D
7AHCT374PW DH
20
20
20
20
PACKAGE
SO
TSSOP
SO
TSSOP
L
L
H
H
CP
↑
↑
↑
↑
D
n
I
h
l
h
INTERNAL
FLIP-FLOPS
L
H
L
H
74AHC374;
74AHCT374
OUTPUTS
Q
0
to Q
7
L
H
Z
Z
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT163-1
SOT360-1
1999 Sep 28
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374;
74AHCT374
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA198
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
DC supply voltage
input voltage
output voltage
operating ambient temperature
range
see DC and AC
characteristics per
device
V
CC
= 5 V
±0.5
V
CONDITIONS
MIN.
2.0
0
0
−40
−40
TYP. MAX. MIN.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
4.5
0
0
−40
TYP. MAX.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
V
V
V
°C
74AHCT
UNIT
+125
−40
100
20
−
−
+125
°C
−
20
ns/V
t
r
,t
f
(∆t/∆f) input rise and fall rates
V
CC
= 3.3 V
±0.3
V
−
−
1999 Sep 28
5
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