Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
•
Balanced propagation delays
•
All inputs have Schmitt-trigger actions
•
Inputs accept voltages higher than V
CC
•
Ideal for addressable register applications
•
Data enable for address and data synchronization
•
Eight positive-edge triggered D-type flip-flops
•
See “273” for master reset version
•
See “373” for transparent latch version
•
See “374” for 3-state version
•
For AHC only: operates with CMOS input levels
•
For AHCT only: operates with TTL input levels
•
Specified from
−40
to +85 and from
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
DESCRIPTION
74AHC377; 74AHCT377
The 74AHC/AHCT377 D-type flip-flops are high-speed
silicon-gate CMOS devices and are pin compatible with
low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-triggered,
D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops
simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
TYPICAL
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
propagation delay;
CP to Q
n
maximum clock frequency
input capacitance
power dissipation
capacitance
CONDITIONS
AHC
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
3.9
175
3.0
20
AHCT
4.0
140
3.0
23
ns
MHz
pF
pF
UNIT
2000 Aug 15
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
FUNCTION TABLE
See note 1.
INPUTS
OPERATING MODES
E
load “1”
load “0”
hold (do nothing)
l
l
h
H
Note
1. H = HIGH voltage level;
CP
↑
↑
↑
X
74AHC377; 74AHCT377
OUTPUTS
D
n
h
l
X
X
Q
n
H
L
no change
no change
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
X = don’t care;
↑
= LOW-to-HIGH CP transition.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
PINS
74AHC377D
74AHC377PW
74AHCT377D
74AHCT377PW
PINNING
PIN
1
2, 5, 6, 9, 12, 15, 16 and 19
3, 4, 7, 8, 13, 14, 17 and 18
10
11
20
E
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
SYMBOL
flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
DC supply voltage
DESCRIPTION
data enable input (active LOW)
20
20
20
20
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT163-1
SOT360-1
2000 Aug 15
3
京公网安备 11010802033920号
EEWORLD
