Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FEATURES
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
•
Balanced propagation delays
•
Inputs accepts voltages higher than
V
CC
•
For AHC only:
operates with CMOS input levels
•
For AHCT only:
operates with TTL input levels
•
Output capability: standard
•
I
CC
category: flip-flops
•
Specified from
−40
to +85 and +125
°C.
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs, set (S
D
) and
reset (R
D
) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
f
max
C
I
C
PD
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
3.0 ns.
74AHC74; 74AHCT74
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
nCP to nQ, nQ
nS
D
, nR
D
to nQ, nQ
max. clock frequency
input capacitance
power dissipation
capacitance
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
CONDITIONS
AHC AHCT
C
L
= 15 pF;
V
CC
= 5 V
3.7
3.7
130
V
I
= V
CC
or GND 4.0
12
3.3
3.7
100
4.0
16
ns
ns
MHz
pF
pF
UNIT
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLES
Table 1
See note 1
INPUT
nS
D
L
H
L
Table 2
nR
D
H
L
L
See note 1
INPUT
nS
D
H
H
nR
D
H
H
nCP
↑
↑
nD
L
H
OUTPUT
nQ
n+1
L
H
nQ
n+1
H
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
OUTPUT
nQ
L
H
H
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
1999 Sep 23
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
ORDERING INFORMATION
OUTSIDE
NORTH
AMERICA
74AHC74D
74AHC74PW
74AHCT74D
74AHCT74PW
PINNING
PIN
1 and 13
2 and 12
3 and 11
4 and 10
5 and 9
6 and 8
7
14
SYMBOL
1R
D
and 2R
D
1D and 2D
1CP and 2CP
1S
D
and 2S
D
1Q and 2Q
1Q and 2Q
GND
V
CC
data inputs
74AHC74; 74AHCT74
PACKAGE
NORTH AMERICA
74AHC74D
74AHC74PW DH
74AHCT74D
74AHCT74PW DH
TEMPERATURE
RANGE
−40
to +85
°C
PINS
14
14
14
14
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
DESCRIPTION
asynchronous reset-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
DC supply voltage
handbook, halfpage
1RD
1D
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
MNA417
14 VCC
13 2RD
12 2D
handbook, halfpage
4 10
1SD 2SD
2
12
3
11
SD
1Q
1D
Q
D
2D
2Q
1CP
CP
2CP
FF
1Q
Q
2Q
RD
1RD 2RD
1 13
MNA418
5
9
74
11 2CP
10 2SD
9
2Q
6
8
8 2Q
Fig.1 Pin configuration.
Fig.2 Logic diagram.
1999 Sep 23
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
74AHC
SYMBOL
V
CC
V
I
V
O
T
amb
PARAMETER
DC supply voltage
input voltage
output voltage
operating ambient temperature
see DC and AC
characteristics per
device
V
CC
= 5 V
±0.5
V
CONDITIONS
MIN.
2.0
0
0
−40
−40
74AHC74; 74AHCT74
74AHCT
UNIT
TYP. MAX.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
V
V
V
°C
TYP. MAX. MIN.
5.0
−
−
+25
+25
−
−
5.5
5.5
V
CC
+85
4.5
0
0
−40
+125
−40
100
20
−
−
+125
°C
−
20
ns/V
t
r
,t
f
(∆t/∆f) input rise and fall rates
V
CC
= 3.3 V
±0.3
V
−
−
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
V
I
I
IK
I
OK
I
O
I
CC
T
stg
P
D
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70
°C
the value of P
D
derates linearly with 8 mW/K.
For TSSOP packages: above 60
°C
the value of P
D
derates linearly with 5.5 mW/K.
PARAMETER
DC supply voltage
input voltage
DC input diode current
DC output diode current
DC V
CC
or GND current
storage temperature
power dissipation per package
for temperature range:
−40
to +85
°C;
note 2
V
I
<
−0.5
V; note 1
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V; note 1
CONDITIONS
MIN. MAX. UNIT
−0.5
−0.5
−
−
−
−
−65
−
+7.0
+7.0
−20
±20
±25
±75
500
V
V
mA
mA
mA
mA
mW
DC output source or sink current
−0.5
V < V
O
< V
CC
+ 0.5 V
+150
°C
1999 Sep 23
5
Embedded System
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