5962H9684504QXA datasheet, PDF

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5962H9684504QXA: DescriptionDual-Port SRAM, 4KX9, 55ns, CMOS, PGA-68; Categorystorage storage; File Size523KB，41 Pages; ManufacturerCobham PLC

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5962H9684504QXA Overview

Dual-Port SRAM, 4KX9, 55ns, CMOS, PGA-68

5962H9684504QXA Parametric

Parameter Name	Attribute value
Maker	Cobham PLC
package instruction	PGA, PGA68,11X11
Reach Compliance Code	unknown
Is Samacsys	N
Maximum access time	55 ns
I/O type	COMMON
JESD-30 code	S-XPGA-P68
JESD-609 code	e0
length	29.5 mm
memory density	36864 bit
Memory IC Type	DUAL-PORT SRAM
memory width	9
Number of functions	1
Number of ports	2
Number of terminals	68
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	4KX9
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	PGA
Encapsulate equivalent code	PGA68,11X11
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Qualified
Filter level	MIL-PRF-38535 Class Q
Maximum seat height	7.1 mm
Maximum standby current	0.0004 A
Minimum standby current	2.5 V
Maximum slew rate	0.275 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
total dose	1M Rad(Si) V
width	29.5 mm
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Added Appendix B to allow for the procurement of die. - glg

Changed Table I parameters; tAW, tPWE, tSCE, and tWH, all from

40 ns to 45 ns. ksr

Boilerplate update and part of five year review. tcr

Added new footnote 3/ to Table IA and renumbered the existing

footnotes. ksr

06-02-24

08-04-08

Raymond Monnin

Robert M. Heber

DATE (YR-MO-DAY)

00-10-13

01-02-27

APPROVED

Raymond Monnin

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Gary L. Gross

CHECKED BY

Jeff Bowling

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS

AVAILABLE

FOR USE BY All

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

AMSC N/A

APPROVED BY

Michael. A. Frye

MICROCIRCUIT, MEMORY, DIGITAL, CMOS

4K X 8/9 RADIATION-HARDENED DUAL-PORT

STATIC RANDOM ACCESS MEMORY (SRAM),

MONOLITHIC SILICON

DRAWING APPROVAL DATE

96-07-30

REVISION LEVEL

SIZE

SHEET

CAGE CODE

67268

1 OF

5962-96845

5962-E235-08

DSCC FORM 2233

APR 97

2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)

ASTM Standard F1192-00

Standard Guide for the Measurement of Single Event Phenomena Induced by

Heavy Ion Irradiation of Semiconductor Devices.

(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor

Drive, West Conshohocken, PA 19428-2959;

http://www.astm.org.)

ELECTRONICS INDUSTRIES ASSOCIATION (EIA)

JEDEC Standard EIA/JESD 78

IC Latch-Up Test.

(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA

22201;

http://www.jedec.org.)

(Non-Government standards and other publications are normally available from the organizations that prepare or distribute

the documents. These documents also may be available in or through libraries or other informational services.)

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-

38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in

the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M

shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device

class M.

3.2.1 Case outlines. The case outlines shall be in accordance with figure 1.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.

3.2.3 Truth table. The truth table shall be as specified on figure 3.

3.2.4 AC test circuit and waveforms. The ac test circuit and waveforms shall be as specified on figure 4.

3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 5.

3.2.6 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns

cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed.

For device class M, alternate test patterns shall be maintained under document revision level control by the manufacturer and

shall be made available to the preparing or acquiring activity upon request. For device classes Q and V alternate test patterns

shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and

shall be made available to the preparing or acquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96845

SHEET

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required

in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in

MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to

this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain

the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 41 (see MIL-PRF-38535, appendix A).

4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in

accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)

electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.

The test circuit shall be maintained by the manufacturer under document revision level control and shall be made

available to the preparing or acquiring activity upon request. For device class M, the test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015.

(1) Dynamic burn-in for device class M (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-96845

SHEET

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