74ALVC164245
16-bit dual supply translating transciever; 3-state
Rev. 02 — 1 June 2004
Product data sheet
1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nA ports to nB ports. nDIR (active LOW) enables
data from nB ports to nA ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nA and nB ports by placing them in a high-impedance OFF-state. The nB
ports interface with the 5 V bus. The nA ports interface with the 3 V bus.
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The A-outputs must be set 3-state and
the voltage on the A-bus must be smaller than V
diode
(typical 0.7 V). V
CCB
≥
V
CCA
(except
in suspend mode).
2. Features
s
5 V tolerant inputs/outputs for interfacing with 5 V logic
s
Wide supply voltage range:
x
3 V port (V
CCA
): 1.5 V to 3.6 V
x
5 V port (V
CCB
): 1.5 V to 5.5 V.
s
CMOS low power consumption
s
Direct interface with TTL levels
s
Control inputs voltage range from 2.7 V to 5.5 V
s
Inputs accept voltages up to 5.5 V
s
High-impedance outputs when V
CCA
or V
CCB
= 0 V
s
Complies with JEDEC standard JESD8-B/JESD36
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V.
s
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
Philips Semiconductors
74ALVC164245
16-bit dual supply translating transceiver; 3-state
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns.
Symbol
Parameter
Conditions
C
L
= 50 pF;
V
CCB
= 4.5 V to 5.5 V;
V
CCA
= 3.0 V to 3.6 V
C
L
= 50 pF;
V
CCB
= 4.5 V to 5.5 V;
V
CCA
= 3.0 V to 3.6 V
C
L
= 50 pF;
V
CCB
= 3.0 V to 3.6 V;
V
CCA
= 2.3 V to 2.7 V
C
L
= 50 pF;
V
CCB
= 3.0 V to 3.6 V;
V
CCA
= 2.3 V to 2.7 V
Min
-
Typ
2.9
Max
-
Unit
ns
t
PHL
, t
PLH
propagation delay nAn
to nBn
propagation delay nBn
to nAn
propagation delay nAn
to nBn
propagation delay nBn
to nAn
C
I
C
I/O
input capacitance
input/output
capacitance A and B
port
power dissipation
capacitance 5 V port:
nAn to nBn
power dissipation
capacitance 3 V port:
nBn to nA
[1]
-
2.5
-
ns
-
3.3
-
ns
-
3.0
-
ns
-
-
4.0
5.0
-
-
pF
pF
C
PD
V
CCB
= 5 V; V
CCA
= 3.3 V
outputs enabled
outputs disabled
V
CCB
= 5 V; V
CCA
= 3.3 V
outputs enabled
outputs disabled
[1] [2]
-
-
[1] [2]
30
15
40
5
-
-
-
-
pF
pF
pF
pF
-
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
[2]
The condition is V
I
= GND to V
CC
.
4. Ordering information
Table 2:
Ordering information
Temperature range Package
Name
74ALVC164245DGG
−40 °C
to +125
°C
74ALVC164245DL
−40 °C
to +125
°C
TSSOP48
SSOP48
Description
plastic thin shrink small outline package; 48 leads;
body width 6.1 mm
plastic shrink small outline package; 48 leads; body
width 7.5 mm
Version
SOT362-1
SOT370-1
Type number
9397 750 13248
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2004
2 of 19
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