74ALVCH16373T datasheet, PDF - EEWORLD Datasheet

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74ALVCH16373T: DescriptionLow Voltage 16-Bit Transparent Latch with Bushold; Categorylogic logic; File Size95KB，7 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74ALVCH16373T Overview

Low Voltage 16-Bit Transparent Latch with Bushold

74ALVCH16373T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP48,.3,20
Contacts	48
Reach Compliance Code	unknow
series	ALVC/VCX/A
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	12.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.024 A
Humidity sensitivity level	2
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP48,.3,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	3.9 ns
propagation delay (tpd)	7.8 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6.1 mm
Base Number Matches	1

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74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold

October 2001

Revised February 2002

74ALVCH16373

Low Voltage 16-Bit Transparent Latch with Bushold

General Description

The ALVCH16373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The ALVCH16373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The 74ALVCH16373 is designed for low voltage (1.65V to

3.6V) V

applications with output compatibility up to 3.6V.

The 74ALVCH16373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

1.65V to 3.6V V

supply operation

3.6V tolerant control inputs and outputs

Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

to O

)

3.6 ns max for 3.0V to 3.6V V

4.5 ns max for 2.3V to 2.7V V

6.8 ns max for 1.65V to 1.95V V

Uses patented noise/EMI reduction circuitry

Latch-up conforms to JEDEC JED78

ESD performance:

Human body model

2000V

Machine model

200V

Ordering Code:

Order Number

74ALVCH16373T

Package

Number

MTD48

Package Description

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

DS500631

www.fairchildsemi.com

74ALVCH16373T Related Products

	74ALVCH16373T	74ALVCH16373
Description	Low Voltage 16-Bit Transparent Latch with Bushold	Low Voltage 16-Bit Transparent Latch with Bushold

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