Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16600
FEATURES
•
Complies with JEDEC standard no. 8-1A.
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Current drive
±
24 mA at 3.0 V
•
All inputs have bus hold circuitry
•
Output drive capability 50Ω transmission lines @ 85°C
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and ground pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH16600 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CP
AB
. When OE
AB
is Low, the outputs are
active. When OE
AB
is High, the outputs are in the high-impedance
state. The High clock can be controlled with the clock-enable inputs
(CE
BA
/CE
AB
).
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
.
To ensure the high impedance state during power up or power
down, OE
BA
and OE
AB
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
= 2.5ns
SYMBOL
t
PHL
/t
PLH
C
I/O
C
I
C
PD
PARAMETER
Propagation delay
An, Bn to Bn, An
Input/Output capacitance
Input capacitance
Power dissipation capacitance per latch
V
I
= GND to V
CC1
Outputs enabled
Outputs disabled
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
TYPICAL
3.1
2.8
8.0
4.0
21
3
UNIT
ns
pF
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
mW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH16600 DGG
DWG NUMBER
SOT364-1
1998 Sep 24
2
853-2123 20077
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16600
LOGIC DIAGRAM
(one section)
OE
AB
CE
AB
LE
AB
CP
AB
CP
BA
LE
BA
CE
BA
OE
BA
A1
CE
C1
CP
1D
B1
CE
C1
CP
1D
18 IDENTICAL CHANNELS
SW00131
FUNCTION TABLE
INPUTS
CE
XX
X
X
X
H
L
L
L
L
XX
H
L
h
l
X
↓
NC
Z
=
=
=
=
=
=
=
=
=
OE
XX
H
L
L
L
L
L
L
L
LE
XX
X
H
H
L
L
L
L
L
CP
XX
X
X
X
X
↓
↓
H
L
DATA
X
H
L
X
h
l
X
X
OUTPUTS
Z
H
L
NC
H
L
NC
Disabled
Transparent
Hold
Clock + display
Hold
STATUS
AB for A-to-B direction, BA for B-to-A direction
HIGH voltage level
LOW voltage level
HIGH state must be present one setup time before the LOW-to-HIGH transition of CP
XX
LOW state must be present one setup time before the LOW-to-HIGH transition of CP
XX
Don’t care
HIGH-to-LOW level transition
No change
High impedance “off” state
1998 Sep 24
4
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