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5962F0422901QZA

Description
Field Programmable Gate Array, 3200000 Gates, 1536-Cell, CMOS, CBGA484, CERAMIC, LGA-484
CategoryProgrammable logic devices    Programmable logic   
File Size378KB,38 Pages
ManufacturerCobham PLC
Download Datasheet Parametric View All

5962F0422901QZA Overview

Field Programmable Gate Array, 3200000 Gates, 1536-Cell, CMOS, CBGA484, CERAMIC, LGA-484

5962F0422901QZA Parametric

Parameter NameAttribute value
MakerCobham PLC
package instructionBGA, LGA484,22X22,50
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Combined latency of CLB-Max1.92 ns
JESD-30 codeS-CBGA-B484
JESD-609 codee0
length29 mm
Equivalent number of gates3200000
Number of entries316
Number of logical units1536
Output times316
Number of terminals484
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize3200000 GATES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeBGA
Encapsulate equivalent codeLGA484,22X22,50
Package shapeSQUARE
Package formGRID ARRAY
power supply2.5,3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class Q
Maximum seat height2.95 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
total dose300k Rad(Si) V
width29 mm
Base Number Matches1
REVISIONS
LTR
DESCRIPTION
Add QML-Q device type 03 with additional screening called out in
section 4. Low Temperature Operating Life (LTOL) test added to
section 4. Correction to section 1.3, remove paragraph 3.12. Added
oscillator test to Table I, also changed leakage current I
IN2
for F rad
hard devices from minimum of -20
μA
to -50
μA,
and a maximum of 5
μA,
to -50
μA.
Made changes to footnotes 1/ 3/, and 4/of Table I. ksr
Made changes to Table I Vol and V
OH
condition blocks, significant
change to I
CC
and I
CCIO
. Added a new footnote 5/ to Table I and
renumbered the rest of the original footnotes. Changed the A3
dimension on both packages X and Y. Removed figure 5. ksr
DATE (YR-MO-DA)
APPROVED
A
06-08-25
Raymond Monnin
B
08-02-08
Robert M. Heber
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
B
35
B
15
B
36
B
16
B
37
B
17
B
18
REV
SHEET
PREPARED BY
Kenneth Rice
CHECKED BY
Raj Pithadia
B
19
B
20
B
21
B
1
B
22
B
2
B
23
B
3
B
24
B
4
B
25
B
5
B
26
B
6
B
27
B
7
B
28
B
8
B
29
B
9
B
30
B
10
B
31
B
11
B
32
B
12
B
33
B
13
B
34
B
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
APPROVED BY
Raymond Monnin
DRAWING APPROVAL DATE
05-09-06
REVISION LEVEL
B
MICROCIRCUIT, MEMORY, DIGITAL, CMOS,
FIELD PROGRAMMABLE GATE ARRAY
(FPGA) 320K GATES with 24 dual-port SRAM
modules, RADIATION HARDENED,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
SHEET
67268
1 OF
37
5962-04229
DSCC FORM 2233
APR 97
5962-E184-08
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