V 1, V 2 V 1, V 2 6.0 V; AGND = DGND = AGND = DGND = 0 V; T = T to T unless
referred 50
DD
DD
DD
DD
P
P
RF1
RF1
RF2
RF2
A
MIN
MAX
1
Parameter
RF/IF CHARACTERISTICS (3 V)
RF1 Input Frequency (RF1
IN
)
ADF4206
ADF4207
ADF4208
RF Input Sensitivity
IF Input Frequency (RF2
IN
)
ADF4206
ADF4207/ADF4208
IF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency
3
RF CHARACTERISTICS (5 V)
RF1 Input Frequency (RF1
IN
)
ADF4206
ADF4207
ADF4208
RF Input Sensitivity
IF Input Frequency (RF2
IN
)
ADF4206
ADF4207/ADF4208
IF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency
3
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
4
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
5
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
I
CP
Three-State Leakage Current
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
V
DD
1
V
DD
2
V
P
I
DD
(I
DD
1 + I
DD
2)
6
ADF4206
ADF4207
ADF4208
I
DD
1
ADF4206
ADF4207
ADF4208
I
DD
2
ADF4206
ADF4207
ADF4208
I
P
(I
P
1 + I
P
2)
Low-Power Sleep Mode
B Version
B Chips
2
Unit
Test Conditions/Comments
See Figure 2 for input circuit.
Use a square wave for frequencies lower than f
MIN
.
0.05/0.55
0.08/1.1
0.08/2.0
–15/+4
0.05/0.55
0.08/1.1
–15/+4
165
0.05/0.55
0.08/1.1
0.08/2.0
–15/+4
0.05/0.55
0.08/1.1
–15/+4
165
GHz min/max
GHz min/max
GHz min/max
dBm min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
Use a square wave for frequencies lower than f
MIN
.
0.05/0.55
0.08/1.1
0.08/2.0
–10/+4
0.05/0.55
0.08/1.1
–10/+4
200
0.05/0.55
0.08/1.1
0.08/2.0
–10/+4
0.05/0.55
0.08/1.1
–10/+4
200
GHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz min/max
GHz min/max
GHz min/max
dBm min/max
MHz max
5/40
–2
10
±
100
55
5/40
–2
10
±
100
55
MHz min/max
dBm min
pF max
µA
max
MHz max
For f < 5 MHz Use Square Wave 0 to V
DD
AC-Coupled. When DC-Coupled,
0 to V
DD
Max (CMOS-Compatible)
5
1.25
2.5
1
0.8
×
V
DD
0.2
×
V
DD
±
1
10
V
DD
– 0.4
0.4
2.7/5.5
V
DD
1
V
DD
1/6.0
14
16.5
21
8
9
14
7.5
8.5
9
1
0.5
5
1.25
2.5
1
0.8
×
V
DD
0.2
×
V
DD
±
1
10
V
DD
– 0.4
0.4
2.7/5.5
V
DD
1
V
DD
1/6.0
14
16.5
21
8
9
14
7.5
8.5
9
1
0.5
mA typ
mA typ
% typ
nA typ
V min
V max
µA
max
pF max
V min
V max
V min/V max
V min/V max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
µA
typ
V
DD
1, V
DD
2
V
P
1, V
P
2
6.0 V
I
OH
= 500
µA
I
OL
= 500
µA
9.5 mA Typical at V
DD
= 3 V, T
A
= 25°C
11 mA Typical at V
DD
= 3 V, T
A
= 25°C
14 mA Typical at V
DD
= 3 V, T
A
= 25°C
5.5 mA Typical at V
DD
= 3 V, T
A
= 25°C
6 mA Typical at V
DD
= 3 V, T
A
= 25°C
9 mA Typical at V
DD
= 3 V, T
A
= 25°C
5 mA Typical at V
DD
= 3 V, T
A
= 25°C
5.5 mA Typical at V
DD
= 3 V, T
A
= 25°C
5.5 mA Typical at V
DD
= 3 V, T
A
= 25°C
T
A
= 25°C
–2–
REV. 0
ADF4206/ADF4207/ADF4208
Parameter
NOISE CHARACTERISTICS
Phase Noise Floor (RF1)
7
ADF4206
ADF4207
ADF4208
ADF4206
ADF4207
ADF4208
Phase Noise Performance
8
ADF4206 (RF1, RF2)
ADF4207 (RF1, RF2)
ADF4207 (RF1, RF2)
9
ADF4208 (RF1)
ADF4208 (RF1)
ADF4208 (RF1)
10
ADF4208 (RF2)
Spurious Signals
RF1, RF2 (20 kHz Loop B/W)
RF1, RF2 (1 kHz Loop B/W)
B Version
B Chips
2
Unit
Test Conditions/Comments
–169
–171
–173
–160
–162
–164
–92
–90
–81
–85
–91
–66
–89
–80/–84
–65/–73
–169
–171
–173
–160
–162
–164
–92
–90
–81
–85
–91
–66
–89
–80/–84
–65/–73
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dB typ
dB typ
@ 25 kHz PFD Frequency
@ 25 kHz PFD Frequency
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 540 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 836 MHz, 30 kHz at PFD
@ 1750 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 1750 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 200 kHz/400 kHz and 200 kHz PFD
@10 kHz/20 kHz and 10 kHz PFD
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is
less than this value.
4
V
DD
1 = V
DD
2 = 3 V; For V
DD
1 = V
DD
2 = 5 V, use CMOS-compatible levels.
5
Guaranteed by design. Sample tested to ensure compliance.
6
Typical values apply for V
DD
= 3 V; P = 32; RF1
IN
1/RF2
IN
2 for ADF4206 = 540 MHz; RF1
IN
1/RF2
IN
2 for ADF4207 = 900 MHz; RF1
IN
1/RF2
IN
2 for ADF4208 = 900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8
The phase noise is measured at a 1 kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation
Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset Frequency = 300 Hz; f
RF/IF
= 836 MHz; N = 27866; Loop B/W = 3 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset Frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
Specifications subject to change without notice.
REV. 0
–3–
ADF4206/ADF4207/ADF4208
(V 1 = V 2 = 3 V 10%, 5 V
TIMING CHARACTERISTICS
AGND = DGND = 0 V; T = T
DD
DD
RF2
RF2
A
10%; V
DD
1, V
DD
2
≤
V
P
1, V
P
2
≤
6.0 V; AGND
RF1
= DGND
RF1
=
.)
MIN
to T
MAX
unless otherwise noted, dBm referred to 50
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
Limit at
T
MIN
to T
MAX
(B Version)
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.
t
3
CLOCK
t
4
t
1
DATA
DB21 (MSB)
DB20
t
2
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
t
5
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted.)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
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