INTEGRATED CIRCUITS
74F273A
Octal D flip-flop
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
FEATURES
•
High impedance inputs for reduced loading
(20
µ
A in Low and High states)
•
Ideal buffer for MOS microprocessor or memory
•
Eight edge–triggered D–type flip–flops
•
Buffered common clock
•
Buffered asynchronous Master Reset
•
See 74F377A for clock enable version
•
See 74F373 for transparent latch version
•
See 74F374 for 3–State version
DESCRIPTION
The 74F273 has eight edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
setup time before the Low–to–High clock transition, is transferred to
the corresponding flip–flop’s Q output.
All outputs will be forced Low independently of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common to all elements.
TYPE
74F273A
TYPICAL
f
MAX
170MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
25mA
ORDERING INFORMATION
PACKAGES
20–pin plastic DIP
20–pin plastic SOL
COMMERCIAL RANGE
V
CC
= 5V±10%;
T
amb
= 0°C to +70°C
74F273AN
74F273AD
PKG. DWG. #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0 – D7
MR
CP
Q0 – Q7
Data inputs
Master Reset input (active–Low)
Clock pulse input (active rising edge)
Data outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
PIN CONFIGURATION
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
LOGIC SYMBOL
3
4
7
8
13
14
17
18
D0
11
1
CP
MR
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND 10
2
V
CC
= Pin 20
GND = Pin 10
5
6
9
12
15
16
19
SF00346
SF00347
1996 Mar 12
2
853–0066 16555
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
LOGIC SYMBOL (IEEE/IEC)
1
11
R
C1
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
SF00348
LOGIC DIAGRAM
D0
3
11
CP
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
CP
R
D
1
MR
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
V
CC
= Pin 20
GND = Pin 10
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SF00349
FUNCTION TABLE
INPUTS
MR
L
H
H
H
h
L
l
X
↑
=
=
=
=
=
=
CP
X
↑
↑
Dn
X
h
l
OUTPUTS
Q0 – Q7
L
H
L
Reset (clear)
Load ”1”
Load ”0”
OPERATING
MODE
High voltage level
High voltage level one set–up time prior to the Low–to–High clock transition
Low voltage level
Low voltage level one set–up time prior to the Low–to–High clock transition
Don’t care
Low–to–High clock transition
1996 Mar 12
3
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
Low–level output current
Operating free air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
LIMITS
TYP
5.0
MAX
5.5
V
V
V
mA
mA
mA
UNIT
°
C
1996 Mar 12
4
Philips Semiconductors
Product specification
Octal D flip–flop
74F273A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
MR & CP
V
OH
High-level output voltage
inputs
other
inputs
V
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
Low-level output voltage
TEST
CONDITIONS
1
V
CC
= MIN, V
IL
= 0.0V
3
,
V
IH
= 4.5V
3
, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
Input clamp voltage
Input current at maximum input voltage
High–level input current
Low–level input current
Short–circuit output current
4
Supply current (total)
I
CCH
I
CCL
V
CC
= MIN, I
I
= I
IK
V
CC
= 0.0V, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
-60
24
27
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
MIN
2.5
2.7
2.5
2.7
3.4
0.30
0.30
–0.73
0.50
0.50
-1.2
100
20
–20
-150
38
43
3.4
LIMITS
TYP
2
MAX
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
UNIT
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. To reduce the effect of external noise during test.
4. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
AC CHARACTERISTICS FOR ’F273A
LIMITS
T
amb
= +25°C
V
CC
= +5.0V
C
L
= 50pF
R
L
= 500Ω
Min
f
MAX
t
PLH
t
PHL
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn
Propagation delay
MR to Qn
1
1
2
150
3.5
5.0
5.0
Typ
170
5.0
7.0
7.0
8.0
9.5
9.0
Max
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±10%
C
L
= 50pF
R
L
= 500Ω
Min
125
3.0
4.5
5.0
9.0
10.0
9.5
Max
MHz
ns
ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
1996 Mar 12
5
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