MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9447/D
Rev 2, 04/2003
3.3V/2.5V 1:9 LVCMOS Clock
Fanout Buffer
The MPC9447 is a 3.3V or 2.5V compatible, 1:9 clock fanout buffer
targeted for high performance clock tree applications. With output
frequencies up to 350 MHz and output skews less than 150 ps, the device
meets the needs of most demanding clock applications.
Features
•
9 LVCMOS Compatible Clock Outputs
MPC9447
•
•
•
•
2 Selectable, LVCMOS Compatible Inputs
Maximum Clock Frequency of 350 MHz
Maximum Clock Skew of 150 ps
LOW VOLTAGE
3.3 V/2.5 V LVCMOS 1:9
CLOCK FANOUT BUFFER
Synchronous Output Stop in Logic Low State Eliminates Output Runt
Pulses
•
High–Impedance Output Control
•
•
•
•
•
3.3V or 2.5V Power Supply
Drives up to 18 Series Terminated Clock Lines
Ambient Temperature Range –40
_
C to +85
_
C
32 Lead LQFP Packaging
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
Supports Clock Distribution in Networking, Telecommunications, and
Computer Applications
•
Pin and Function Compatible to MPC947
Functional Description
MPC9447 is specifically designed to distribute LVCMOS compatible
clock signals up to a frequency of 350 MHz. Each output provides a
precise copy of the input signal with a near zero skew. The outputs buffers
support driving of 50 terminated transmission lines on the incident
edge: each is capable of driving either one parallel terminated or two
series terminated transmission lines.
Two selectable independent LVCMOS compatible clock inputs are available, providing support of redundant clock source
systems. The MPC9447 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the
output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the
outputs into high–impedance mode.
All inputs have an internal pull–up or pull–down resistor preventing unused and open inputs from floating. The device supports
a 2.5V or 3.3V power supply and an ambient temperature range of –40
_
C to +85
_
C. The MPC9447 is pin and function compatible
but performance–enhanced to the MPC947.
W
©
Motorola, Inc. 2003
MPC9447
GND
GND
GND
17
16
15
14
13
GND
Q6
VCC
Q7
GND
Q8
VCC
GND
12
11
10
9
1
2
3
4
5
6
7
8
1
CLK1 input selected
Outputs enabled
Outputs active
GND
Condition
Per output
Inputs
VCC
VCC
18
Unit
V
V
V
mA
10
4.0
pF
pF
VCC
Q3
Q4
Q5
19
OE
Q0
CCLK0
CCLK1
VCC
0
1
CLK
STOP
24
Q1 GND
Q2
Q3
CLK_SEL
VCC
SYNC
Q6 VCC
GND
Q7
VCC
(all input resistors have a value of 25k )
CLK_SEL
CCLK0
CCLK1
Max
GND
OE
CLK_STOP
Q8
31
32
Q4
Q5
CLK_STOP
Q1
GND
Q0
28
Q2
VCC
25
26
27
23
22
21
20
MPC9447
29
30
W
Figure 1. Logic Diagram
Figure 2. 32–Lead Pinout
(Top View)
Table 1. Function Table
Control
CLK_SEL
OE
CLK_STOP
Default
1
1
1
CLK0 input selected
Outputs disabled (high–impedance state)a
Outputs synchronously stopped in logic low state
0
a. OE = 0 will high–impedance tristate all outputs independent on CLK_STOP
Table 2. Pin Configuration
Pin
CCLK0
CCLK1
CLK_SEL
CLK_STOP
OE
Q0–8
GND
VCC
I/O
Input
Input
Input
Input
Input
Output
Supply
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
Clock signal input
Alternative clock signal input
Clock input select
Clock output enable/disable
Output enable/disable (high–impedance tristate)
Clock outputs
Negative power supply (GND)
Positive power supply for I/O and core. All VCC pins must be
connected to the positive power supply for correct operation
Function
Table 3. General Specifications
Symbol
VTT
MM
HBM
LU
CPD
CIN
Characteristics
Output termination voltage
ESD protection (Machine model)
ESD protection (Human body model)
Latch-up immunity
Power dissipation capacitance
Input capacitance
200
2000
200
Min
Typ
VCC
÷
2
MOTOROLA
2
TIMING SOLUTIONS
MPC9447
Table 4. Absolute Maximum Ratingsa
Symbol
VCC
VIN
VOUT
IIN
IOUT
TS
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
-65
Characteristics
Min
-0.3
-0.3
-0.3
Max
3.9
VCC + 0.3
VCC + 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics
(VCC = 3.3V
±
5%, TA = 40°C to +85°C)
Symbol
VIH
VIL
VOH
VOL
ZOUT
IIN
ICCQ
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Currentb
Maximum Quiescent Supply Currentc
17
±300
2.0
Min
2.0
–0.3
2.4
0.55
0.30
Typ
Max
VCC + 0.3
0.8
Unit
V
V
V
V
V
Condition
LVCMOS
LVCMOS
IOH = -24 mAa
IOL = 24 mA
IOL = 12 mA
VIN = VCC or GND
All VCC Pins
W
µA
mA
a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for
VCC=3.3V).
b. Inputs have pull-down or pull-up resistors affecting the input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 6. AC Characteristics
(VCC = 3.3V
±
5%, TA = –40°C to +85°C)a
Symbol
fref
fmax
fP,REF
tr, tf
tPLH/HL
tPLZ, HZ
tPZL, ZH
tS
tH
tsk(O)
tsk(PP)
tSK(P)
DCQ
tr, tf
tJIT(CC)
Input Frequency
Output Frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
Propagation Delay
Output Disable Time
Output Enable Time
Setup Time
Hold Time
Output-to-Output Skew
Device-to-Device Skew
Output Pulse Skewd
Output Duty Cycle
Output Rise/Fall Time
Cycle-to-cycle jitter
RMS (1
σ)
CCLK0 or CCLK1 to CLK_STOPc
CCLK0 or CCLK1 to CLK_STOPc
0.0
1.0
150
2.0
fQ<170 MHz
45
0.1
TBD
50
300
55
1.0
CCLK0 or CCLK1 to any Q
1.3
5Characteristics
Min
0
0
1.4
1.0b
3.3
11
11
Typ
Max
350
350
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ps
ns
ps
%
ns
ps
DCREF = 50%
0.55 to 2.4V
0.8 to 2.0V
Condition
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
c. Setup and hold times are referenced to the falling edge of the selected clock signal input.
d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
TIMING SOLUTIONS
3
MOTOROLA
MPC9447
Table 7. DC Characteristics
(VCC = 2.5V
±
5%, TA = –40°C to +85°C)
Symbol
VIH
VIL
VOH
VOL
ZOUT
IIN
ICCQ
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Currentb
Maximum Quiescent Supply Currentc
19
±300
2.0
Min
1.7
-0.3
1.8
0.6
Typ
Max
VCC + 0.3
0.7
Unit
V
V
V
V
Condition
LVCMOS
LVCMOS
IOH =-15 mAa
IOL = 15 mA
VIN = VCC or GND
All VCC Pins
W
µA
mA
a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines per output
(VCC=2.5V).
b. Inputs have pull-down or pull-up resistors affecting the input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 8. AC Characteristics
(VCC = 2.5V
±
5%, TA =
–
40°C to +85°C)a
Symbol
fref
fmax
fP,REF
tr, tf
tPLH/HL
tPLZ, HZ
tPZL, ZH
tS
tH
tsk(O)
tsk(PP)
tSK(P)
DCQ
tr, tf
tJIT(CC)
Input Frequency
Output frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
Propagation Delay
Output Disable Time
Output Enable Time
Setup Time
Hold Time
Output-to-Output Skew
Device-to-Device Skew
Ouput Pulse Skewd
Output Duty Cycle
Output Rise/Fall Time
Cycle-to-cycle jitter
RMS (1
σ)
CCLK0 or CCLK1 to CLK_STOPc
CCLK0 or CCLK1 to CLK_STOPc
0.0
1.0
150
2.7
fQ<350 MHz
45
0.1
TBD
50
200
55
1.0
CCLK0 or CCLK1 to any Q
1.7
Characteristics
Min
0
0
1.4
1.0b
4.4
11
11
Typ
Max
350
350
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ps
ns
ps
%
ns
ps
DCREF = 50%
0.6 to 1.8V
0.7 to 1.7V
Condition
a. AC characteristics apply for parallel output termination of 50Ω to VTT.
b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
c. Setup and hold times are referenced to the falling edge of the selected clock signal input.
d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
MOTOROLA
4
TIMING SOLUTIONS
MPC9447
APPLICATION INFORMATION
Figure 3. Output Clock Stop (CLK_STOP) Timing
Diagram
CCLK0 or
CCLK1
CLK_STOP
VOLTAGE (V)
Q0 to Q8
3.0
OutA
tD = 3.8956
OutB
tD = 3.9386
2.5
2.0
In
1.5
Driving Transmission Lines
The MPC9447 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17Ω (VCC=3.3V), the
outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Motorola application note
AN1091. In most high performance clock networks,
point–to–point distribution of signals is the method of choice.
In a point–to–point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50Ω resistance to VCC
÷2.
1.0
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Line Termination
Waveforms
The waveform plots in Figure 5 “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases,
the drive capability of the MPC9447 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations
a delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output–to–output skew
of the MPC9447. The output waveform in Figure 5 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 33Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL
Z0
RS
R0
VL
= VS ( Z0
÷
(RS+R0 +Z0))
= 50Ω || 50Ω
= 33Ω || 33Ω
= 17Ω
= 3.0 ( 25
÷
(16.5+17+25)
= 1.28V
MPC9447
OUTPUT
BUFFER
IN
17Ω
RS = 33Ω
ZO = 50Ω
OutA
MPC9447
OUTPUT
BUFFER
IN
17Ω
RS = 33Ω
ZO = 50Ω
OutB0
RS = 33Ω
ZO = 50Ω
OutB1
Figure 4. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9447 clock driver. For the series
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 4 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9447 clock driver is effectively doubled
due to its capability to drive multiple lines at VCC=3.3V.
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines, the
situation in Figure 6 “Optimized Dual Line Termination”
should be used. In this case, the series terminating resistors
TIMING SOLUTIONS
5
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