APA450-FFGES datasheet, PDF - EEWORLD Datasheet

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APA450-FFGES: DescriptionProASIC Flash Family FPGAs; File Size4MB，174 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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APA450-FFGES Overview

ProASIC Flash Family FPGAs

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v5.7

ProASIC

PLUS®

Flash Family FPGAs

Features and Benefits

High Capacity

Commercial and Industrial

•

75,000 to 1 Million System Gates

27 k to 198 kbits of Two-Port SRAM

66 to 712 User I/Os

300, 000 to 1 million System Gates

72 k to 198 kbits of Two Port SRAM

158 to 712 User I/Os

0.22 µm 4 LM Flash-Based CMOS Process

Live At Power-Up (LAPU) Level 0 Support

Single-Chip Solution

No Configuration Device Required

Retains Programmed Design during Power-Down/Up Cycles

Mil/Aero Devices Operate over Full Military Temperature

Range

3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military

temperature)

Two Integrated PLLs

External System Performance up to 150 MHz

The Industry’s Most Effective Security Key (FlashLock

)

Low Impedance Flash Switches

Segmented Hierarchical Routing Structure

Small, Efficient, Configurable (Combinatorial or Sequential)

Logic Cells

APA075

75,000

3,072

27 k

158

Yes

100, 144

208

–

144

APA150

150,000

6,144

36k

242

Yes

100

208

456

144, 256

APA300

300,000

8,192

72 k

290

Yes

–

208

456

144, 256

208, 352

APA450

450,000

12,288

108 k

344

Yes

–

208

456

144, 256, 484

APA600

600,000

21,504

126 k

454

Yes

–

208

456

256, 484, 676

208, 352

624

APA750

750,000

32,768

144 k

562

Yes

–

208

456

676, 896

High Performance Routing Hierarchy

•

Ultra-Fast Local and Long-Line Network

High-Speed Very Long-Line Network

High-Performance, Low Skew, Splittable Global Network

100% Routability and Utilization

Schmitt-Trigger Option on Every Input

2.5 V/3.3 V Support with Individually-Selectable Voltage and

Slew Rate

Bidirectional Global I/Os

Compliance with PCI Specification Revision 2.2

Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant

Pin Compatible Packages across the ProASIC

PLUS

Family

PLL with Flexible Phase, Multiply/Divide and Delay

Capabilities

Internal and/or External Dynamic PLL Configuration

Two LVPECL Differential Pairs for Clock or Data Inputs

Flexibility with Choice of Industry-Standard Front-End Tools

Efficient Design through Front-End Timing and Gate Optimization

In-System Programming (ISP) via JTAG Port

SmartGen Netlist Generation Ensures Optimal Usage of

Embedded Memory Blocks

24 SRAM and FIFO Configurations with Synchronous and

Asynchronous Operation up to 150 MHz (typical)

I/O

Military

Reprogrammable Flash Technology

Unique Clock Conditioning Circuitry

Standard FPGA and ASIC Design Flow

ISP Support

SRAMs and FIFOs

Performance

•

Secure Programming

Low Power

Table 1 •

ProASIC

PLUS

Product Profile

Device

Maximum System Gates

Tiles (Registers)

Embedded RAM Bits (k=1,024 bits)

Embedded RAM Blocks (256x9)

LVPECL

PLL

Global Networks

Maximum Clocks

Maximum User I/Os

JTAG ISP

PCI

Package (by pin count)

TQFP

PQFP

PBGA

FBGA

CQFP

CCGA/LGA

Notes:

APA1000

1,000,000

56,320

198 k

712

Yes

–

208

456

896, 1152

208, 352

624

1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.

2. These packages are available only for Military/MIL-STD-883B devices.

S e pt em be r 2 0 08

See the Actel website for the latest version of the datasheet.

ProASIC

PLUS

Flash Family FPGAs

Table of Contents

General Description

ProASIC

PLUS

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33

Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-44

1-46

1-48

1-50

Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50

Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51

Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51

Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73

Recommended Design Practice for V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74

Package Pin Assignments

100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

v5.7

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