ADVANCE INFORMATION
Am29LV640MU
64 Megabit (4 M x 16-Bit) MirrorBit
3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Single power supply operation
— 3 V for read, erase, and program operations
s
VersatileI/O control
— Device generates data output voltages and tolerates
data input voltages on the CE# and DQ inputs/outputs
as determined by the voltage on the V
IO
pin; operates
from 1.65 to 3.6 V
s
Manufactured on 0.23 µm MirrorBit process
technology
s
SecSi (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
s
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
s
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
s
Minimum 100,000 erase cycle guarantee per sector
s
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
s
High performance
— 90 ns access time
— 25 ns page read times
— 0.4 s typical sector erase time
— 5.9 µs typical write buffer word programming time:
16-word write buffer reduces overall programming
time for multiple-word/byte updates
— 4-word page read buffer
— 16-word write buffer
s
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
s
Package options
— 63-ball Fine-Pitch BGA
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
s
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: r ead/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
s
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— ACC (high voltage) input accelerates programming
time for higher throughput during system production
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) indicates program or
erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.4/26/02
Publication#
25301
Rev:
B
Amendment/+1
Issue Date:
April 26, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV640MU is a 64 Mbit, 3.0 volt single power
supply flash memory device organized as 4,194,304
words. The device has a 16-bit only data bus, and can
be programmed either in the host system or in stan-
dard EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
CC
) and an I/O voltage range (V
IO
), as
specified in the
Product Selector Guide
and the
Order-
ing Information
sections. The device is offered in a
63-ball Fine-Pitch BGA or 64-ball Fortified BGA pack-
age. Each device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
IO
pin.
Refer to the
Ordering Information
section for valid V
IO
options.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The
Program
Suspend/Program Resume
feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power c ons umption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi (Secured Silicon) Sector
provides a
128-word area for code or data that can be perma-
nently protected. Once this sector is protected, no fur-
ther changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV640MU
April 26, 2002
A D V A N C E
I N F O R M A T I O N
MIRRORBIT 64 MBIT DEVICE FAMILY
Device
LV065MU
LV640MT/B
LV640MH/L
LV641MH/L
LV640MU
Bus
x8
x8/x16
x8/x16
x16
x16
Sector Architecture
Uniform (64 Kbyte)
Boot (8 x 8 Kbyte
at top & bottom)
Uniform (64 Kbyte)
Uniform (32 Kword)
Uniform (32 Kword)
Packages
48-pin TSOP (std. & rev. pinout),
63-ball FBGA
48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA
56-pin TSOP (std. & rev. pinout),
64 Fortified BGA
48-pin TSOP (std. & rev. pinout)
63-ball Fine-pitch BGA
V
IO
Yes
No
Yes
Yes
Yes
RY/BY#
Yes
Yes
Yes
No
Yes
WP#, ACC
ACC only
WP#/ACC pin
WP#/ACC pin
Separate WP#
and ACC pins
ACC only
WP# Protection
No WP#
2 x 8 Kbyte
top or bottom
1 x 64 Kbyte
high or low
1 x 32 Kword
top or bottom
No WP#
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com
→
Flash Memory
→
Prod-
uct Information
→
MirrorBit
→
Flash Information
→
Tech-
nical Documentation.
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
AMD MirrorBit™ White Paper
Migrating from Single-byte to Three-byte Device IDs
M i g r a t i o n f r o m A m 2 9 LV 6 4 0 D U t o M i r r o r B i t
Am29LV640MU
April 26, 2002
Am29LV640MU
3
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
MirrorBit 64 Mbit Device Family . . . . . . . . . . . . . . 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions .................................... 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
Figure 6. Erase Operation.............................................................. 30
Command Definitions ............................................................. 31
Table 10. Command Definitions...................................................... 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling ................................................................. 32
Figure 7. Data# Polling Algorithm .................................................. 32
RY/BY#: Ready/Busy#............................................................ 33
DQ6: Toggle Bit I .................................................................... 33
Figure 8. Toggle Bit Algorithm........................................................ 34
VersatileIO (V
IO
) Control ..................................................... 10
Requirements for Reading Array Data ................................... 10
Page Mode Read .................................................................... 11
Writing Commands/Command Sequences ............................ 11
Write Buffer ............................................................................. 11
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Sector Address Table ........................................................13
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 34
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
DQ1: Write-to-Buffer Abort ..................................................... 35
Table 11. Write Operation Status ................................................... 35
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 36
Figure 9. Maximum Negative Overshoot Waveform ..................... 36
Figure 10. Maximum Positive Overshoot Waveform..................... 36
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Autoselect Mode..................................................................... 15
Table 3. Autoselect Codes, (High Voltage Method) .......................15
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
Figure 12. Input Waveforms and
Measurement Levels...................................................................... 38
Sector Group Protection and Unprotection ............................. 16
Table 4. Sector Group Protection/Unprotection Address Table .....16
Temporary Sector Group Unprotect ....................................... 17
Figure 1. Temporary Sector Group Unprotect Operation................ 17
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 13. Read Operation Timings ............................................... 39
Figure 14. Page Read Timings ...................................................... 40
SecSi (Secured Silicon) Sector Flash Memory Region .......... 19
Table 5. SecSi Sector Contents ......................................................19
Hardware Reset (RESET#) .................................................... 41
Figure 15. Reset Timings ............................................................... 41
Hardware Data Protection ...................................................... 19
Low VCC Write Inhibit ............................................................ 19
Write Pulse “Glitch” Protection ............................................... 20
Logical Inhibit .......................................................................... 20
Power-Up Write Inhibit ............................................................ 20
Common Flash Memory Interface (CFI) . . . . . . . 20
Table 6. CFI Query Identification String .............................. 20
Table 7. System Interface String......................................................21
Erase and Program Operations .............................................. 42
Figure 16. Program Operation Timings..........................................
Figure 17. Accelerated Program Timing Diagram..........................
Figure 18. Chip/Sector Erase Operation Timings ..........................
Figure 19. Data# Polling Timings
(During Embedded Algorithms)......................................................
Figure 20. Toggle Bit Timings
(During Embedded Algorithms)......................................................
Figure 21. DQ2 vs. DQ6.................................................................
43
43
44
45
46
46
Table 8. Device Geometry Definition................................... 21
Table 9. Primary Vendor-Specific Extended Query............. 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . 22
Reading Array Data ................................................................ 22
Reset Command ..................................................................... 23
Autoselect Command Sequence ............................................ 23
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23
Word Program Command Sequence ..................................... 23
Unlock Bypass Command Sequence ..................................... 24
Write Buffer Programming ...................................................... 24
Accelerated Program .............................................................. 25
Figure 3. Write Buffer Programming Operation............................... 26
Figure 4. Program Operation .......................................................... 27
Temporary Sector Unprotect .................................................. 47
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 47
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 48
Alternate CE# Controlled Erase and Program Operations ..... 49
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 50
Program Suspend/Program Resume Command Sequence ... 27
Figure 5. Program Suspend/Program Resume............................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Erase And Programming Performance. . . . . . . . 51
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 51
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52
LAA064—64-Ball Fortified Ball Grid Array (FBGA)
13 x 11 mm Package .............................................................. 52
FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
12 x 11 mm Package .............................................................. 53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 54
4
Am29LV640MU
April 26, 2002
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
V
CC
= 3.0–3.6 V
Speed Option
V
CC
= 2.7–3.6 V
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (t
PACC
)
Max. OE# Access Time (ns)
90
90
25
25
90R
(V
IO
= 3.0–3.6 V)
101
(V
IO
= 2.7–3.6 V)
100
100
30
30
112
(V
IO
= 1.65–3.6 V)
110
110
40
40
120
(V
IO
= 1.65–3.6 V)
120
120
40
40
Am29LV640MU
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
V
IO
RESET#
WE#
ACC
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ0
–
DQ15
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A21–A0
April 26, 2002
Am29LV640MU
5
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