Am29DL16xD
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
21533
Revision
E
Amendment
+4
Issue Date
May 26, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29DL16xD
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
■
Multiple bank architectures
— Four devices available with different bank sizes (refer
to Table 2)
■
SecSi™ (Secured Silicon) Sector
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
■
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
■
Package options
— 48-ball Very Thin Profile Fine-pitch BGA
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
— 48-pin TSOP
■
Top or bottom boot block
■
Manufactured on 0.23 µm process technology
— Compatible with Am29DL16xC devices
■
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Minimum 1 million write cycles guaranteed per sector
■
20 Year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming
and erasing, enabling EEPROM emulation
— Eases sector erase limitations
■
Supports Common Flash Memory Interface (CFI)
■
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to reading array data
■
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21533
Rev:
E
Amendment/+4
Issue Date:
May 26, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29DL16xD family consists of 16 megabit, 3.0
volt-only flash memory devices, organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each.
Word mode data appears on DQ0–DQ15; byte mode
data appears on DQ0–DQ7. The device is designed to
be programmed in-system with the standard 3.0 volt
V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70, 90,
or 120 ns. The devices are offered in 48-pin TSOP,
48-ball Fine-pitch BGA, 48-ball Very Thin Profile
Fine-pitch BGA, and 64-ball Fortified BGA packages.
Standard control pins—chip enable (CE#), write en-
able (WE#), and output enable (OE#)—control normal
read and write operations, and avoid bus contention
issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s y s te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
May 26, 2004
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL16xD devices uses multiple bank archi-
tectures to provide flexibility for different applications.
Four devices are available with these bank sizes:
Device
DL161
DL162
DL163
DL164
Bank 1
0.5 Mb
2 Mb
4 Mb
8 Mb
Bank 2
15.5 Mb
14 Mb
12 Mb
8 Mb
Am29DL16xD Features
The
SecSi™
(Secured Silicon) Sector is an extra sec-
tor capable of being permanently locked by AMD or
customers. The
SecSi Sector Indicator Bit
(DQ7) is
permanently set to a 1 if the part is
factory locked,
and set to a 0 if
customer lockable.
This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Current version of device has 64
Kbytes; future versions will have only 256 bytes.
This should be considered during system design.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
4
Am29DL16xD
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .......................................... 9
Sector Erase Command Sequence .............................................. 27
Erase Suspend/Erase Resume Commands ................................ 28
Figure 4. Erase Operation .................................................................... 28
Command Definitions ................................................................... 29
Table 14. Am29DL16xD Command Definitions .................................... 29
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 11
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 12
Table 1. Am29DL16xD Device Bus Operations ....................................12
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling ...................................................................... 30
Figure 5. Data# Polling Algorithm ......................................................... 30
Word/Byte Configuration .............................................................. 12
Requirements for Reading Array Data .........................................12
Writing Commands/Command Sequences .................................. 13
Accelerated Program Operation ...............................................13
Autoselect Functions .................................................................13
Simultaneous Read/Write Operations with Zero Latency ............13
Standby Mode .............................................................................. 13
Automatic Sleep Mode .................................................................13
RESET#: Hardware Reset Pin .....................................................14
Output Disable Mode ...................................................................14
Table 2. Am29DL16xD Device Bank Divisions .....................................14
Table 3. Sector Addresses for Top Boot Sector Devices ......................15
Table 4. SecSi™ Sector Addresses for Top Boot Devices .................. 15
Table 5. Sector Addresses for Bottom Boot Sector Devices .................16
Table 6. SecSi™ Addresses for Bottom Boot Devices ........................ 16
RY/BY#: Ready/Busy# ................................................................. 31
DQ6: Toggle Bit I .......................................................................... 31
Figure 6. Toggle Bit Algorithm .............................................................. 31
DQ2: Toggle Bit II ......................................................................... 32
Reading Toggle Bits DQ6/DQ2 .................................................... 32
DQ5: Exceeded Timing Limits ...................................................... 32
DQ3: Sector Erase Timer ............................................................. 32
Table 15. Write Operation Status ......................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 7. Maximum Negative Overshoot Waveform ............................. 34
Figure 8. Maximum Positive Overshoot Waveform ............................. 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents)..................................................................................... 36
Figure 10. Typical I
CC1
vs. Frequency................................................... 36
Autoselect Mode .......................................................................... 17
Table 7. Am29DL16xD Autoselect Codes, (High Voltage Method) ......17
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup .......................................................................... 37
Table 16. Test Specifications ................................................................ 37
Sector/Sector Block Protection and Unprotection ........................ 18
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................18
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................18
Key To Switching Waveforms ...................................................... 37
Figure 12. Input Waveforms and Measurement Levels ........................ 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Read Operation Timings...................................................... 38
Figure 14. Reset Timings...................................................................... 39
Write Protect (WP#) .....................................................................19
Temporary Sector/Sector Block Unprotect ...................................19
Figure 1. Temporary Sector Unprotect Operation ................................. 19
Figure 2. In-System Sector/Sector Block Protection and
Unprotection Algorithms........................................................................ 20
Word/Byte Configuration (BYTE#) ............................................... 40
Figure 15. BYTE# Timings for Read Operations .................................. 40
Figure 16. BYTE# Timings for Write Operations .................................. 40
Erase and Program Operations ................................................... 41
Figure 17. Program Operation Timings ................................................
Figure 18. Accelerated Program Timing Diagram ................................
Figure 19. Chip/Sector Erase Operation Timings .................................
Figure 20. Back-to-back Read/Write Cycle Timings .............................
Figure 21. Data# Polling Timings (During Embedded Algorithms) .......
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............
Figure 23. DQ2 vs. DQ6 .......................................................................
42
42
43
44
44
45
45
SecSi™ (Secured Silicon) Sector Flash Memory Region ............21
Factory Locked: SecSi Sector Programmed and Protected At the
Factory ......................................................................................21
Customer Lockable: SecSi Sector NOT Programmed or
Protected At the Factory ...........................................................21
Hardware Data Protection ............................................................ 21
Low VCC Write Inhibit ...............................................................22
Write Pulse “Glitch” Protection .................................................. 22
Logical Inhibit ............................................................................22
Power-Up Write Inhibit .............................................................. 22
Temporary Sector/Sector Block Unprotect ................................... 46
Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram 46
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 47
Alternate CE# Controlled Erase and Program Operations ........... 48
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 49
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 10. CFI Query Identification String ..............................................
Table 11. System Interface String.........................................................
Table 12. Device Geometry Definition ..................................................
Table 13. Primary Vendor-Specific Extended Query ............................
22
23
23
24
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ...................................................................... 25
Reset Command .......................................................................... 25
Autoselect Command Sequence .................................................. 25
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ....26
Byte/Word Program Command Sequence ...................................26
Unlock Bypass Command Sequence .......................................26
Figure 3. Program Operation ................................................................ 27
Erase And Programming Performance . . . . . . .
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
Package and Pin Capacitance . . . . . . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
50
50
50
FBC048—48-Ball Fine-Pitch Ball Grid Array
8 x 9 mm package ........................................................................ 51
LAA064—64-Ball Fortified Ball Grid Array,
13 x 11 mm package .................................................................... 52
TS 048—48-Pin Standard TSOP ................................................. 53
VBF048—48-Ball Very Thin Profile Fine-Pitch Ball Grid Array .... 54
Chip Erase Command Sequence .................................................27
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
May 26, 2004
Am29DL16xD
5
FPGA/CPLD
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