MCM69F737TQ8 datasheet, PDF - EEWORLD Datasheet

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MCM69F737TQ8: DescriptionCache SRAM, 128KX36, 8ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size280KB，20 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MCM69F737TQ8 Overview

Cache SRAM, 128KX36, 8ns, CMOS, PQFP100, TQFP-100

MCM69F737TQ8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
package instruction	TQFP-100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	8 ns
Other features	OPTIONAL INTERLEAVED OR LINEAR BURST; BYTE WRITE CONTROL; SELF TIMED WRITE CYCLE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of ports	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM69F737/D

128K x 36 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F737 is a 4M bit synchronous fast static RAM designed to provide

a burstable, high performance, secondary cache for the PowerPC™ and other

high performance microprocessors. It is organized as 128K words of 36 bits

each. This device integrates input registers, a 2–bit address counter, and high

speed SRAM onto a single monolithic circuit for reduced parts count in cache

data RAM applications. Synchronous design allows precise cycle control with the

use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F737 (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F737 operates from a 3.3 V core power supply and all outputs

operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

•

MCM69F737–7.5: 7.5 ns Access/8.5 ns Cycle (117 MHz)

MCM69F737–8: 8 ns Access/10 ns Cycle (100 MHz)

MCM69F737–8.5: 8.5 ns Access/11ns Cycle (90 MHz)

MCM69F737–11: 11 ns Access/20 ns Cycle (50 MHz)

•

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

•

ADSP, ADSC, and ADV Burst Control Pins

•

Selectable Burst Sequencing Order (Linear/Interleaved)

•

Single–Cycle Deselect Timing

•

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

•

PB1 Version 2.0 Compatible

•

JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

MCM69F737

ZP PACKAGE

PBGA

CASE 999–02

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 7

1/22/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F737

MCM69F737TQ8 Related Products

	MCM69F737TQ8	MCM69F737TQ11R	MCM69F737TQ11
Description	Cache SRAM, 128KX36, 8ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 128KX36, 11ns, CMOS, PQFP100, TQFP-100	Cache SRAM, 128KX36, 11ns, CMOS, PQFP100, TQFP-100
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )
package instruction	TQFP-100	TQFP-100	TQFP-100
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	8 ns	11 ns	11 ns
Other features	OPTIONAL INTERLEAVED OR LINEAR BURST; BYTE WRITE CONTROL; SELF TIMED WRITE CYCLE	OPTIONAL INTERLEAVED OR LINEAR BURST; BYTE WRITE CONTROL; SELF TIMED WRITE CYCLE	OPTIONAL INTERLEAVED OR LINEAR BURST; BYTE WRITE CONTROL; SELF TIMED WRITE CYCLE
JESD-30 code	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	e0	e0	e0
length	20 mm	20 mm	20 mm
memory density	4718592 bit	4718592 bit	4718592 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	36	36	36
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	100	100	100
word count	131072 words	131072 words	131072 words
character code	128000	128000	128000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C
organize	128KX36	128KX36	128KX36
Output characteristics	3-STATE	3-STATE	3-STATE
Exportable	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP	LQFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm

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