AGL125V5-VQG144ES datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> AGL125V5-VQG144ES

AGL125V5-VQG144ES: DescriptionFPGA, 24576 CLBS, 1000000 GATES, 108 MHz, PBGA144; Categorysemiconductor Programmable logic devices; File Size6MB，212 Pages; ManufacturerActel; Websitehttp://www.actel.com/

Download Datasheet Parametric View All

AGL125V5-VQG144ES Overview

FPGA, 24576 CLBS, 1000000 GATES, 108 MHz, PBGA144

AGL125V5-VQG144ES Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.14 V
Rated supply voltage	1.2 V
Processing package description	13 X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, HALOGEN FREE AND ROHS COMPLIANT, FBGA-144
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, LOW PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN SILVER COPPER
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
organize	24576 CLBS, 1000000 GATES
Maximum FCLK clock frequency	108 MHz
Number of configurable logic modules	24576
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	1.00E6

Preview

Download Datasheet

View All

v1.3

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low-Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

Mode

•

Advanced I/O

•

700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X

, and

LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os

‡

Programmable Output Slew Rate

and Drive Strength

Weak Pull-Up/-Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the IGLOO Family

High Capacity

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except ARM

-enabled IGLOO

devices) via JTAG (IEEE 1532–compliant)

• FlashLock

to Secure FPGA Contents

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

ARM Processor Support in IGLOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

AGL060

60 k

512

1,536

Yes

CS121

QN132

VQ100

FG144

AGL125

125 k

1,024

3,072

Yes

133

CS196

QN132

VQ100

FG144

AGL250

AGL400

AGL600

AGL1000

M1AGL250 M1AGL400 M1AGL600 M1AGL1000

250 k

400 k

600 k

2,048

–

6,144

9,216

13,824

24,576

108

144

Yes

143

194

235

300

CS196

QN132

4,5

VQ100

FG144

CS196

CS281

IGLOO Product Family

IGLOO Devices

ARM-Enabled IGLOO Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

UC/CS

QFN

VQFP

FBGA

AGL015

15 k

128

384

–

QN68

AGL030

30 k

256

768

–

UC81/CS81

QN48, QN68,

QN132

VQ100

FG144,

FG256,

FG484

FG144,

FG256,

FG484

FG144,

FG256,

FG484

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

AGL060 in CS121 does not support the PLL.

Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

The M1AGL250 device does not support this package.

Device/package support TBD

For higher densities and support of additional features, refer to the

IGLOOe Low-Power Flash FPGAs with Flash*Freeze

Technology

handbook.

‡ Supported only by AGL015 and AGL030 devices.

1 AGL015 and AGL030 devices do not support this feature.

December 2008

1 – IGLOO Device Family Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-

power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery

to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)

while the IGLOO device is completely functional in the system. This allows the IGLOO device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,

single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and

AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,

supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.

M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM

for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA

fabric. It has a three-stage pipeline that offers a good balance between low-power consumption

and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction

set, has a configurable nested interrupt controller, and can be implemented with or without the

debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.

The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support

AES decryption.

Flash*Freeze Technology

The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off

I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of

IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction

in power consumption, thus achieving the lowest total system power.

When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks

and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and

data is retained.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices

the best fit for portable electronics.

v1.3

1-1

Recommended Resources

Car glass hail melting circuit design

Automatic temperature control circuit a composed of TWH9205 integrated circuit

Simple inverter circuit diagram

Guangshun KYT1-40A turning fan circuit diagram

Control circuit of 15D display in counter

Computer motherboard circuit diagram 815 3_12

Sneak peek at the latest 3G home smart robot project!: As the Internet of Things technology, 3G communication technology, multimedia technology, and electromechanical control technology become more and more mature, products based on related technologies a...; yazi Robotics Development

Technological innovation promotes outdoor diagnosis and treatment: [align=left][color=rgb(85, 85, 85)][font="][size=14px][color=rgb(204, 0, 0)][url=http://e2echina.ti. com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-01-15/2043.1.jpg][img]http...; alan000345 TI Technology Forum

Double T notch filter s-domain calculation analysis (pure manual calculation, engineering version!): [size=4]Author: eeworld netizen zjd01--Zhang Jindong[/size][size=4]Original link: [url=https://user.qzone.qq.com/37564275/blog/1471793060]S-domain calculation and analysis of double-T notch filter (pu...; okhxyyo Analog electronics

【MicroPython】+ Radio-controlled clock: [i=s]This post was last edited by jameswoo on 2016-4-17 11:40[/i] Following the steps of the masters, I also started working on my radio-controlled clock. Many people have posted pictures of the board...; jameswoo MicroPython Open Source section

We see that body fat detection, high-frequency radio frequency circuits, or ultrasonic detection all use sine waves instead of triangle waves,...: [i=s]This post was last edited by QWE4562009 on 2021-12-8 19:14[/i]We see that body fat detection, high-frequency radio frequency circuits, or ultrasonic detection all choose to use sine waves instead...; QWE4562009 Discrete Device

It is recommended that the website remove the verification code function for members: For members of this website, it can save the trouble of entering verification codes, which makes communication more convenient...; bw120wxj FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components