BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
Rev. 03 — 18 June 2010
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance Architecture (HPA) TrenchPLUS technology,
featuring very low on-state resistance, integrated current sensing transistors and over
temperature protection diodes.
1.2 Features and benefits
Integrated current sensors
Integrated temperature sensors
1.3 Applications
Lamp switching
Motor drive systems
Power distribution
Solenoid drivers
1.4 Quick reference data
Table 1.
Symbol
R
DSon
Quick reference data
Parameter
drain-source
on-state
resistance
ratio of drain
current to sense
current
drain-source
breakdown
voltage
Conditions
V
GS
= 5 V; I
D
= 10 A;
T
j
= 25 °C; see
Figure 15;
see
Figure 16
T
j
= 25 °C; V
GS
= 5 V;
see
Figure 17
I
D
= 250 µA; V
GS
= 0 V;
T
j
= 25 °C
Min
-
Typ
9.8
Max Unit
11.5
mΩ
FET1 and FET2 static characteristics
I
D
/I
sense
6193 6881 7569 A/A
V
(BR)DSS
65
-
-
V
NXP Semiconductors
BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pinning information
Symbol Description
G1
IS1
D1
A1
C1
G2
IS2
D2
A2
C2
D2
KS2
S2
S2
D2
D1
KS1
S1
S1
D1
gate 1
current sense 1
drain
anode 1
cathode 1
gate 2
current sense 2
drain 2
anode 2
cathode 2
drain 2
Kelvin source 2
source 2
source 2
drain 2
drain 1
Kelvin source 1
source 1
source 1
drain 1
1
10
G1
IS1 S1 KS1 C1 G2
IS2 S2 KS2 C2
003aaa745
Simplified outline
20
11
Graphic symbol
D1
A1
D2
A2
FET1
FET2
SOT163-1 (SO20)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9MHH-65PNN
SO20
Description
plastic small outline package; 20 leads; body width 7.5 mm
Version
SOT163-1
Type number
BUK9MHH-65PNN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 18 June 2010
2 of 16
NXP Semiconductors
BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
4. Limiting values
Table 4.
Symbol
FET1 and FET2
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
V
isol(FET-TSD)
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
FET to temperature
sense diode isolation
voltage
source current
peak source current
non-repetitive
drain-source
avalanche energy
electrostatic discharge
voltage
T
sp
= 25 °C
pulsed; t
p
≤
10 µs; T
sp
= 25 °C
I
D
= 15.1 A; V
sup
= 65 V; V
GS
= 5 V;
T
j(init)
= 25 °C; unclamped; see
Figure 3
[4][5][6]
[1][3]
Limiting values
Parameter
Conditions
25 °C
≤
T
j
≤
150 °C
R
GS
= 20 kΩ; 25 °C
≤
T
j
≤
150 °C
V
GS
= 5 V; T
sp
= 25 °C; see
Figure 1
V
GS
= 5 V; T
sp
= 100 °C; see
Figure 1
T
sp
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 4
T
sp
= 25 °C; see
Figure 2
[1][2]
[1][2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Min
-
-
-15
-
-
-
-
-55
-55
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
65
65
15
15
9.5
319
5
150
150
100
Unit
V
V
V
A
A
A
W
°C
°C
V
FET1 and FET2 source-drain diode
I
S
I
SM
E
DS(AL)S
-
-
-
-
-
-
7
319
878
A
A
mJ
FET1 and FET2 avalanche ruggedness
FET1 and FET2 electrostatic discharge
V
ESD
HBM; C = 100 pF; R = 1.5 kΩ; all pins
HBM; C = 100 pF; R = 1.5 kΩ; pins 8,
11 and 15 to pins 6, 7, 12, 13 and 14
shorted
HBM; C = 100 pF; R = 1.5 kΩ; pins 3,
16 and 20 to pins 1, 2, 17, 18 and 19
shorted
[1]
[2]
[3]
[4]
[5]
[6]
Single device conducting.
Continuous current is limited by package.
Current is limited by chip power dissipation rating.
Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.
Repetitive rating defined in avalanche rating figure.
Refer to application note AN10273 for further information.
-
-
-
-
0.15
4
kV
kV
-
-
4
kV
BUK9MHH-65PNN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 18 June 2010
3 of 16
NXP Semiconductors
BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
16
I
D
(A)
12
001aal615
120
P
der
(%)
80
003aab388
8
40
4
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
200
T
sp
(°C)
Fig 1.
Continuous drain current as a function of
solder point temperature, FET1 and FET2
Fig 2.
Normalized total power dissipation as a
function of solder point temperature, FET1 and
FET2
001aal679
10
2
I
AL
(A)
(1)
10
(2)
1
(3)
10
−1
10
−3
10
−2
10
−1
1
t
AL
(ms)
10
Fig 3.
Single-Pulse and repetitive avalanche rating; avalanche current as a function of avalanche time.
BUK9MHH-65PNN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 18 June 2010
4 of 16
NXP Semiconductors
BUK9MHH-65PNN
Dual TrenchPLUS FET Logic Level FET
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
001aal760
t
p
= 10
μs
100
μs
10
1
DC
10
−1
1 ms
10 ms
100 ms
10
−2
10
−1
1
10
V
DS
(V)
10
2
Fig 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
Conditions
FET1
FET2
mounted on a printed-circuit board; both
channels conducting; zero heat sink
area; see
Figure 5
mounted on a printed-circuit board; both
channels conducting; 200 mm² copper
heat sink area; see
Figure 6
mounted on a printed-circuit board; both
channels conducting; 400 mm² copper
heat sink area; see
Figure 7
mounted on a printed-circuit board; one
channel conducting; zero heat sink
area; see
Figure 5
mounted on a printed-circuit board; one
channel conducting; 200 mm² copper
heat sink area; see
Figure 6
mounted on a printed-circuit board; one
channel conducting; 400 mm² copper
heat sink area; see
Figure 7
Min
-
-
-
Typ
-
-
73
Max
25
25
-
Unit
K/W
K/W
K/W
R
th(j-a)
-
60
-
K/W
-
51
-
K/W
-
105
-
K/W
-
90
-
K/W
-
70
-
K/W
BUK9MHH-65PNN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 18 June 2010
5 of 16
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