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ASM3I623S00EG-16-SR

Description
PLL Based Clock Driver, 3I Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16
Categorylogic    logic   
File Size293KB,16 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Environmental Compliance  
Download Datasheet Parametric View All

ASM3I623S00EG-16-SR Overview

PLL Based Clock Driver, 3I Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, GREEN, SOIC-16

ASM3I623S00EG-16-SR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeSOIC
package instructionSOP,
Contacts16
Reach Compliance Codeunknown
Is SamacsysN
series3I
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.905 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)250
propagation delay (tpd)0.35 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.25 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3.9 mm
Base Number Matches1
July 2005
rev 1.0
ASM3P623S00A/B/C/D/E/F
Zero Cycle Slip Peak EMI reduction IC
General Features
Input frequency range: 20MHz - 50MHz.
Zero input - output propagation delay.
Low-skew outputs.
Output-output skew less than 250pS.
Device-device skew less than 700pS.
Less than 200pS cycle-to-cycle jitter is compatible
with Pentium
®
based systems.
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S00D/E/F), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S00A/B/C).
3.3V operation
Advanced 0.35µ CMOS technology.
The First True Drop-in Solution.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S00D/E/F devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Please refer
Differential Cycle Slips and Spread Spectrum
Control Table” for deviations and differential Cycle Slips
for ASM3P623S00A/B/C and the ASM3P623S00D/E/F
devices
Functional Description
ASM3P623S00D/E/F is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out eight low-skew clocks. It is
available in a 16pin package. The ASM3P623S00A/B/C is
the eight-pin version of the ASM3P623S00. It accepts one
reference input and drives out one low-skew clock.
The ASM3P623S00A/B/C and the ASM3P623S00D/E/F
are available in two different configurations, as shown in
the ordering information table.
Block Diagram
V
DD
SSON
SS%
Modulation
Reference
Divider
Feedback
Divider
PLL
CLKIN
Phase
Detector
Loop
Filter
VCO
Feedforward
Divider
CLKOUT
V
SS
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
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