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MC10H602FN

Description
TTL to ECL Translator, 1 Func, True Output, BIPolar, PQCC28, PLASTIC, LCC-28
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size86KB,4 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

MC10H602FN Overview

TTL to ECL Translator, 1 Func, True Output, BIPolar, PQCC28, PLASTIC, LCC-28

MC10H602FN Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMotorola ( NXP )
package instructionQCCJ, LDCC28,.5SQ
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
maximum delay
Input propertiesSTANDARD
Interface integrated circuit typeTTL TO ECL TRANSLATOR
JESD-30 codeS-PQCC-J28
JESD-609 codee0
length11.5062 mm
Number of digits9
Number of functions1
Number of terminals28
Maximum operating temperature75 °C
Minimum operating temperature
Output characteristicsOPEN-EMITTER
Output latch or registerLATCH
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
power supply5,-5.2 V
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum slew rate50 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
Supply voltage 1-max-5.46 V
Mains voltage 1-minute-4.94 V
Supply voltage1-Nom-5.2 V
surface mountYES
technologyBIPOLAR
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
width11.5062 mm
Base Number Matches1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9-Bit Latch TTL/ECL
Translator
The MC10H/100H602 is a 9–bit, dual supply TTL to ECL translator with
latch. Devices in the Motorola 9–bit translator series utilize the 28–lead
PLCC for optimal power pinning, signal flow–through and electrical
performance.
The H602 features D–type latches. Latching is controlled by Latch
Enable (LEN), while the Master Reset input resets the latches. A
post–latch logic enable is also provided (ENECL), allowing control of the
output state without destroying latch data. All control inputs are ECL level.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
9–Bit Ideal for Byte–Parity Applications
Flow–Through Configuration
Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
Dual Supply
3.5 ns Max D to Q
PNP TTL Inputs for Low Loading
MC10H602
MC100H602
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
PIN NAMES
PIN
GND
VCCE
VCCO
VCCT
VEE
D0 – D8
Q0 – Q8
ENECL
LEN
MR
FUNCTION
TTL Ground (0 V)
ECL VCC (0 V)
ECL VCC (0 V) — Outputs
TTL Supply (+ 5.0 V)
ECL Supply (– 5.2 / – 4.5 V)
Data Inputs (TTL)
Data Outputs (ECL)
Enable Control (ECL)
Latch Enable (ECL)
Master Reset (ECL)
LOGIC SYMBOL
ENECL
D0
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
DQ
EN
Q0
D1
Q1
TRUTH TABLE
D
LEN
L
L
H
X
X
MR
L
L
L
H
X
ENECL
H
H
H
H
L
Q
L
H
Q0
L
L
D2
Q2
D3
Q3
L
H
X
X
X
ECL
TTL
D4
Q4
Pinout: 28–Lead PLCC
(Top View)
Q5
D6
26
27
28
D5
D5 D4 VCCT D3
25
24
23
22
D2 D1 D0
21
20
19
18
17
16
15
D6
Q0
Q1
VCCE
VCCO
Q2
VCCO
Q3
Q6
D7
D8
D7
Q7
GND
MR
2
3
4
5
6
7
8
9
10
11
14
13
12
D8
LEN
MR
Q8
LEN
ENECL
Q8 Q7 VCCO Q6 VEE Q5 Q4
3/93
©
Motorola, Inc. 1996
2–307
REV 5

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