Philips Semiconductors
Product specification
Dual 4-channel analog multiplexer,
demultiplexer
FEATURES
•
Wide analog input voltage range from
−5
V to +5 V
•
Low ON-resistance:
– 80
Ω
(typical) at V
CC
−
V
EE
= 4.5 V
– 70
Ω
(typical) at V
CC
−
V
EE
= 6.0 V
– 60
Ω
(typical) at V
CC
−
V
EE
= 9.0 V
•
Logic level translation: to enable 5 V logic to
communicate with
±5
V analog signals
•
Typical “break before make” built in
•
Complies with JEDEC standard no. 7A
•
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C.
APPLICATIONS
•
Analog multiplexing and demultiplexing
•
Digital multiplexing and demultiplexing
•
Signal gating.
DESCRIPTION
74HC4052; 74HCT4052
The 74HC4052 and 74HCT4052 are high-speed Si-gate
CMOS devices and are pin compatible with the
HEF4052B. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4052 and 74HCT4052 are dual 4-channel
analog multiplexers or demultiplexers with common select
logic. Each multiplexer has four independent
inputs/outputs (pins nY0 to nY3) and a common
input/output (pin nZ). The common channel select logics
include two digital select inputs (pins S0 and S1) and an
active LOW enable input (pin E). When pin E = LOW, one
of the four switches is selected (low-impedance ON-state)
with pins S0 and S1. When pin E = HIGH, all switches are
in the high-impedance OFF-state, independent of pins S0
and S1.
V
CC
and GND are the supply voltage pins for the digital
control inputs (pins S0, S1, and E). The V
CC
to GND
ranges are 2.0 V to 10.0 V for 74HC4052 and
4.5 V to 5.5 V for 74HCT4052. The analog inputs/outputs
(pins nY0 to nY3 and nZ) can swing between V
CC
as a
positive limit and V
EE
as a negative limit. V
CC
−
V
EE
may
not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is
connected to GND (typically ground).
FUNCTION TABLE
INPUT
(1)
CHANNEL BETWEEN
E
L
L
L
L
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care.
S1
L
L
H
H
X
S0
L
H
L
H
X
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
2004 Nov 11
2
Philips Semiconductors
Product specification
Dual 4-channel analog multiplexer,
demultiplexer
QUICK REFERENCE DATA
V
EE
= GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
74HC4052; 74HCT4052
TYPICAL
SYMBOL
t
PZH
/t
PZL
t
PHZ
/t
PLZ
C
I
C
PD
C
S
PARAMETER
turn-on time E or Sn to V
os
turn-off time E or Sn to V
os
input capacitance
power dissipation capacitance per switch notes 1 and 2
maximum switch capacitance
independent (Y)
common (Z)
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ[(C
L
+ C
S
)
×
V
CC2
×
f
o
] where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
C
S
= maximum switch capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
Σ[(C
L
+ C
S
)
×
V
CC2
×
f
o
] = sum of the outputs.
2. For 74HC4052 the condition is V
I
= GND to V
CC
For 74HCT4052 the condition is V
I
= GND to V
CC
−
1.5 V.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74HC4052D
74HCT4052D
74HC4052DB
74HCT4052DB
74HC4052N
74HCT4052N
74HC4052PW
74HC4052BQ
74HCT4052BQ
TEMPERATURE
RANGE
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
PINS
16
16
16
16
16
16
16
16
16
PACKAGE
SO16
SO16
SSOP16
SSOP16
DIP16
DIP16
TSSOP16
DHVQFN16
DHVQFN16
MATERIAL
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
CODE
SOT109-3
SOT109-3
SOT338-1
SOT338-1
SOT38-9
SOT38-9
SOT403-1
SOT763-1
SOT763-1
CONDITIONS
74HC4052 74HCT4052
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
C
L
= 15 pF; R
L
= 1 kΩ;
V
CC
= 5 V
28
21
3.5
57
5
12
18
13
3.5
57
5
12
ns
ns
pF
pF
pF
pF
UNIT
2004 Nov 11
3
Philips Semiconductors
Product specification
Dual 4-channel analog multiplexer,
demultiplexer
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
S1
S0
1Y3
1Y0
1Z
1Y1
1Y2
V
CC
SYMBOL
74HC4052; 74HCT4052
DESCRIPTION
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input
select logic input
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
positive supply voltage
handbook, halfpage
2Y2 2
2Z 3
2Y3 4
15 1Y2
14 1Y1
13 1Z
2Y2
2Z
2Y3
2
3
4
5
6
7
8
GND
S1
9
1
2Y0 1
16 VCC
terminal 1
index area
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
4052
2Y1 5
E 6
VEE 7
GND 8
MNB039
2Y1
E
V
EE
12 1Y0
11 1Y3
10 S0
9
S1
V
CC(1)
2Y0
4052
001aac117
Transparent top view
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration DIP16, SO16 and
(T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2004 Nov 11
4
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