Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
FEATURES
•
8-bit serial input
•
8-bit serial or parallel output
•
Storage register with 3-state outputs
•
Shift register with direct clear
•
100 MHz (typical) shift out frequency
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
APPLICATIONS
•
Serial-to-parallel data conversion
•
Remote control holding register.
DESCRIPTION
74HC595; 74HCT595
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT595 is an 8-stage serial shift register with a
storage register and 3-state outputs. The shift register and
storage register have separate clocks.
Data is shifted on the positive-going transitions of the
SH_CP input. The data in each register is transferred to
the storage register on a positive-going transition of the
ST_CP input. If both clocks are connected together, the
shift register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided
with asynchronous reset (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state
bus driver outputs. Data in the storage register appears at
the output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
SH_CP to Q7’
SH_CP to Qn
MR to Q7’
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC595 the condition is V
I
= GND to V
CC
.
For 74HCT595 the condition is V
I
= GND to V
CC
−
1.5 V.
2003 Jun 25
2
maximum clock frequency SH_CP and ST_CP
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
74HC
C
L
= 50 pF; V
CC
= 4.5 V
19
20
100
100
3.5
115
25
24
52
57
3.5
130
ns
ns
ns
MHz
pF
pF
74HCT
UNIT
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
FUNCTION TABLE
See note 1.
INPUT
SH_CP ST_CP
X
X
X
↑
X
↑
X
X
OE
L
L
H
L
MR
L
L
L
H
DS
X
X
X
H
OUTPUT
74HC595; 74HCT595
FUNCTION
Q7’
L
L
L
Q6’
Qn
n.c.
L
Z
n.c.
a LOW level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance
OFF-state
logic high level shifted into shift register stage 0;
contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Q6’) appears on the
serial output (Q7’)
contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
contents of shift register shifted through; previous
contents of the shift register is transferred to the
storage register and the parallel output stages
X
↑
L
H
X
n.c.
Qn’
↑
↑
L
H
X
Q6’
Qn’
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition;
Z = high-impedance OFF-state;
n.c. = no change;
X = don’t care.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74HC595N
74HCT595N
74HC595D
74HCT595D
74HC595DB
74HCT595DB
74HC595PW
74HCT595PW
74HC595BQ
74HCT595BQ
TEMPERATURE
RANGE
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PINS
16
16
16
16
16
16
16
16
16
16
PACKAGE
DIP16
DIP16
SO16
SO16
SSOP16
SSOP16
TSSOP16
TSSOP16
DHVQFN16
DHVQFN16
MATERIAL
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
CODE
SOT38-4
SOT38-4
SOT109-1
SOT109-1
SOT338-1
SOT338-1
SOT403-1
SOT403-1
SOT763-1
SOT763-1
2003 Jun 25
3
Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q7’
MR
SH_CP
ST_CP
OE
DS
Q0
V
CC
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable (active LOW)
serial data input
parallel data output
positive supply voltage
74HC595; 74HCT595
DESCRIPTION
handbook, halfpage
handbook, halfpage
Q1
1
VCC
16
15
14
13
Q0
DS
OE
ST_CP
SH_CP
MR
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
4
16 VCC
15 Q0
Q2
Q3
2
3
4
14 DS
13 OE
Q4
Q5
Q6
595
5
6
7
12 ST_CP
11 SH_CP
GND
(1)
5
6
7
8
Top view
GND
9
Q7'
MBL893
12
11
10
10 MR
9
MLA001
GND 8
Q7'
Q7
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration DIP16, SO16 and
(T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2003 Jun 25
4
FPGA/CPLD
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