INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT125
Quad buffer/line driver; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
FEATURES
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
74HC/HCT125
The 74HC/HCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled
by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a HIGH impedance OFF-state.
The “125” is identical to the “126” but has active LOW enable inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
9
3.5
22
12
3.5
24
HCT
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
PIN DESCRIPTION
PIN NO.
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
SYMBOL
1OE to 4OE
1A to 4A
1Y to 4Y
GND
V
CC
NAME AND FUNCTION
outputs enable inputs (active LOW)
data inputs
data outputs
ground (0 V)
positive supply voltage
74HC/HCT125
(a)
(b)
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS
nOE
L
L
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
nA
L
H
X
OUTPUT
nY
L
H
Z
Fig.4 Functional diagram.
Fig.5 Logic diagram (one buffer).
December 1990
3
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to +85
−40
to +125
max.
150
30
26
190
38
32
190
38
32
90
18
15
ns
ns
ns
ns
74HC/HCT125
TEST CONDITIONS
UNIT V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
Fig.7
Fig.7
WAVEFORMS
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
nA to nY
30
11
9
t
PZH
/ t
PZL
3-state output enable time
nOE to nY
41
15
12
t
PHZ
/ t
PLZ
3-state output disable time
nOE to nY
41
15
12
t
THL
/ t
TLH
output transition time
14
5
4
100
20
17
125
25
21
125
25
21
60
12
10
125
25
21
155
31
26
155
31
26
75
15
13
Fig.6
December 1990
4
Philips Semiconductors
Product specification
Quad buffer/line driver; 3-state
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
Note to HCT types
74HC/HCT125
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine
∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
nA, nOE
UNIT LOAD COEFFICIENT
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HCT
SYMBOL
PARAMETER
+25
−40
to +85
−40
to +125
max.
38
42
38
18
ns
ns
ns
ns
4.5
4.5
4.5
4.5
Fig.6
Fig.7
Fig.7
Fig.6
UNIT V
CC
(V)
WAVEFORMS
TEST CONDITIONS
min. typ. max. min. max. min.
t
PHL
/ t
PLH
t
PZH
/ t
PZL
t
PHZ
/ t
PLZ
t
THL
/ t
TLH
propagation delay
nA to nY
3-state output enable time
nOE to nY
3-state output disable time
nOE to nY
output transition time
15
15
15
5
25
28
25
12
31
35
31
15
December 1990
5
Analogue and Mixed Signal
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