INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT139
Dual 2-to-4 line
decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
FEATURES
•
Demultiplexing capability
•
Two independent 2-to-4 decoders
•
Multifunction capability
•
Active LOW mutually exclusive outputs
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
74HC/HCT139
The 74HC/HCT139 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). It is specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT139 are high-speed, dual 2-to-4 line
decoder/multiplexers. This device has two independent
decoders, each accepting two binary weighted inputs
(nA
0
and nA
1
) and providing four mutually exclusive active
LOW outputs (nY
0
to nY3). Each decoder has an active
LOW enable input (nE).
When nE is HIGH, every output is forced HIGH. The
enable can be used as the data input for a 1-to-4
demultiplexer application.
The “139” is identical to the HEF4556 of the HE4000B
family.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nA
n
to nY
n
nE
3
to nY
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
APPLICATIONS
•
Memory decoding or data-routing
•
Code conversion
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993
2
input capacitance
power dissipation capacitance per multiplexer
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
10
3.5
42
13
13
3.5
44
ns
ns
pF
pF
HCT
UNIT
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74HC/HCT139
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
nE
H
L
L
L
L
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
nA
0
X
L
H
L
H
nA
1
X
L
L
H
H
nY
0
H
L
H
H
H
OUTPUTS
nY
1
H
H
L
H
H
nY
2
H
H
H
L
H
nY
3
H
H
H
H
L
Fig.5 Logic diagram (one decoder/demultiplexer).
September 1993
4
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nA
n
to Y
n
propagation delay
nE to nY
n
output transition
time
+25
typ.
39
14
11
33
12
10
19
7
6
max.
145
29
25
135
27
23
75
15
13
−40
to
+85
min.
max.
180
36
31
170
34
29
95
19
16
−40
to
+125
min.
max.
220
44
38
205
41
35
110
22
19
ns
UNIT
74HC/HCT139
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Figs 6 and 7
September 1993
5
Embedded System
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