74F38-Q100
Quad 2-input NAND buffer (open collector)
Rev. 1 — 19 May 2014
Product data sheet
1. General description
The 74F38-Q100 provides four 2-input NAND functions with open-collector outputs.
2. Features and benefits
Co
mmercial
range (0C to +70
C)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
N74F38D-Q100
0
C
to +70
C
Name
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
Version
SOT108-1
Type number
NXP Semiconductors
74F38-Q100
Quad 2-input NAND buffer (open collector)
4. Functional diagram
1
2
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
5
2Y
6
9
3Y
8
10
&
8
&
3
&
6
4Y
11
12
13
&
11
mna697
mna698
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration DIP14 and SO14 package
74F38-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
2 of 11
NXP Semiconductors
74F38-Q100
Quad 2-input NAND buffer (open collector)
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
1Y, 2Y, 3Y, 4Y
GND
V
CC
[1]
[2]
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
Unit load
HIGH/LOW
1.0/2.0
1.0/2.0
OC/106.7
-
-
Load value
[1][2]
HIGH/LOW
20
A/1.2
mA
20
A/1.2
mA
OC/64 mA
-
-
One FAST Unit Load (UL) is defined as 20
A
in HIGH state, 0.6 mA in LOW state.
OC = open collector.
6. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
O
T
amb
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output current
ambient temperature
storage temperature
Conditions
[1]
Min
0.5
0.5
0.5
30
-
[2]
Max
+7.0
+7.0
V
CC
+5
128
70
+150
Unit
V
V
V
mA
mA
C
C
output in HIGH-state
V
I
< 0 V
output in LOW-state
in free-air
[1]
0
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
74F38-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
3 of 11
NXP Semiconductors
74F38-Q100
Quad 2-input NAND buffer (open collector)
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
IH
V
IL
V
OH
I
IK
I
OL
Recommended operating conditions
Parameter
supply voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
input clamping current
LOW-level output current
Conditions
Min
4.5
2.0
-
-
18
-
Typ
5.0
-
-
-
-
-
Max
5.5
-
0.8
4.5
-
64
Unit
V
V
V
V
mA
mA
9. Static characteristics
Table 6.
Static characteristics
Conditions
V
CC
= 4.5 V; I
IK
=
18
mA
V
CC
= 4.5 V; V
IL
= 0.8 V; V
IH
= 2.0 V
I
OL
= 64 mA
V
CC
=
10
%
V
CC
=
5
%
I
I
I
IH
I
IL
I
CC
input leakage current
HIGH-level input current
LOW-level input current
supply current
V
CC
= 0 V; V
I
= 7.0 V
V
CC
= 5.5 V; V
I
= 2.7 V
V
CC
= 5.5 V; V
I
= 0.5 V
V
CC
= 5.5 V
V
I
= GND
V
I
= 4.5 V
[1]
All typical values are measured at V
CC
= 5 V.
Symbol Parameter
V
IK
V
OL
input clamping voltage
LOW-level output
voltage
25
C
Min Typ
[1]
Max
1.2 0.73
-
0
C
to +70
C
Min
1.2
Max
-
Unit
V
-
-
-
-
-
-
-
-
0.42
-
-
-
4
22
-
-
-
-
-
-
-
-
-
-
-
20
-
-
0.55
0.55
100
20
-
7
30
V
V
A
A
A
mA
mA
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V. Test circuit is shown in
Figure 6.
Symbol Parameter
Conditions
25
C;
V
CC
= 5.0 V
Min
t
PZL
t
PLZ
OFF-state to LOW
propagation delay
LOW to OFF-state
propagation delay
nA, nB to nY; see
Figure 4
nA, nB to nY; see
Figure 4
1.5
7.5
Typ
3.0
10.0
Max
5.0
12.5
0
C
to +70
C;
V
CC
= 5.0 V
0.5 V
Min
1.5
7.5
Max
5.5
13.0
ns
ns
Unit
74F38-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
4 of 11
NXP Semiconductors
74F38-Q100
Quad 2-input NAND buffer (open collector)
11. Waveforms
V
I
nA, nB input
GND
t
PLZ
V
CC
nY output
V
OL
aaa-010563
V
M
t
PZL
V
M
V
M
V
M
= 1.5 V
VOL is a typical output voltage level that occurs with the output load.
Fig 4.
Propagation delay for inverting outputs
18
Propagation
delay
(ns)
14
12
10
8
6
4
aaa-010521
t
PLZ
t
PZL
2
0
0
200
400
600
Load resistor (Ω)
When using open collector parts, the value of the pull-up resistor greatly affects the value of the t
PLZ
. For example, changing the
specified pull-up resistor value from 500
to 100
improves the t
PLZ
up to 50% with only a slight increase in the t
PZL
.
However, if the value of the pull-up resistor is changed, the user must ensure that the total I
OL
current through the resistor and
the total I
IL
of the receivers, does not exceed the I
OL
minimum specification.
Fig 5.
Typical propagation delays versus load for open collector outputs
74F38-Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 19 May 2014
5 of 11
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