MPR604HSU-02
(IBM Order Number)
MPC604EC/D
(Motorola Order Number)
11/95
REV 1
™
Advance Information
PowerPC 604
™
RISC Microprocessor
Hardware Specifications
The PowerPC 604 microprocessor is an implementation of the PowerPC™ family of
reduced instruction set computer (RISC) microprocessors. This document contains
pertinent physical characteristics of the 604. For information about the functionality of the
604, refer to the
PowerPC 604 RISC Microprocessor Users Manual.
This document contains the following topics:
Topic
Page
In this document, the term “604” is used as an abbreviation for the phrase “PowerPC 604
microprocessor.” The PowerPC 604 microprocessors are available from IBM as PPC604
and from Motorola as MPC604.
The PowerPC name, the PowerPC logotype, and PowerPC 604 are trademarks of International Business Machines Corporation.
FLOTHERM is a registered trademark of Flomerics Ltd., UK.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to
change or discontinue this product without notice.
©
Motorola Inc. 1995
Portions hereof
©
International Business Machines Corp. 1991–1995. All rights reserved.
604 Hardware Specifications
Section 1.1, “General Parameters”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.3, “AC Electrical Characteristics”
Section 1.4, “PowerPC 604 Microprocessor Pin Assignments”
Section 1.5, “PowerPC 604 Microprocessor Pinout Listings”
Section 1.6, “PowerPC 604 Microprocessor Package Description”
Section 1.7, “System Design Information”
Section 1.8, “Thermal Management Information”
Section 1.9, “Ordering Information”
2
2
3
11
14
19
25
27
30
1.1 General Parameters
0.5
µ
m CMOS, four-layer metal
196 mm
2
, 12.4 mm x 15.8 mm
Surface-mount 304-pin C4-CQFP
Surface-mount 255-lead ceramic ball grid array (BGA)
Voltage
3.3 V
±
5%
Maximum power dissipation 24 W @ 133 MHz
19 W @ 100 MHz
Technology
Chip size
Packages
1.2 Electrical and Thermal Characteristics
This section provides both the AC and DC electrical specifications and thermal characteristics for the 604.
The following specifications are preliminary and subject to change without notice. For the most recent
specifications, contact your local Motorola or IBM sales office.
1.2.1 DC Electrical Characteristics
Table 1 and Table 2 provide the absolute maximum rating and thermal characteristics for the 604.
Table 1. PowerPC 604 Microprocessor Absolute Maximum Ratings
Characteristic
Supply voltage
Input voltage
Storage temperature range
Symbol
Vdd
Vin
Tstg
Value
–0.3 to 3.6
–0.3 to 5.5
–55 to 150
Unit
V
V
°
C
Notes:
1. Functional operating conditions are given in DC electrical specifications. Absolute
maximum ratings are stress ratings only, and functional operation at the maximums is
not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2.
Caution:
Input voltage must not be greater than the supply voltage by more than 2.5 V
during power-on reset.
Table 2. PowerPC 604 Microprocessor Thermal Characteristics
Characteristic
C4-CQFP package thermal resistance, junction-to-case
BGA package thermal resistance, junction-to-case
Symbol
θ
JC
θ
JC
Value
0.03
0.03
Rating
°
C/W
°
C/W
Notes
:
1. For the BGA package, the
θ
JC measurement is made from die junction to the back of the
bare silicon die.
2. The junction temperature of the chip is a function of several parameters including
θ
JC.
Please refer to Section 1.8, “Thermal Management Information,” for additional details.
2
Preliminary/Subject to Change without Notice
604 Hardware Specifications
Table 3 provides the DC electrical characteristics for the 604.
Table 3. PowerPC 604 Microprocessor DC Electrical Specifications
Vdd = 3.3
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105
°
C, Input capacitance = 10 pF maximum
Characteristic
Input high voltage (all inputs except SYSCLK)
Input low voltage (all inputs except SYSCLK)
SYSCLK input high voltage
SYSCLK input low voltage
Output high voltage, IOH
= –9
mA
Output low voltage, IOL
= 9
mA
Symbol
VIH
VIL
CVIH
CVIL
VOH
VOL
2
0
2.4
0
2.4
—
Min
Max
5.5
0.8
5.5
0.4
—
0.4
Unit
V
V
V
V
V
V
Table 4 provides the power dissipation numbers for the 604.
Table 4. PowerPC 604 Microprocessor Power Dissipation
Processor Core Frequency
Unit
100 MHz
Full-On Mode
Typical
Maximum
14.5
19.0
17.0
22.5
18.5
24.0
W
W
120 MHz
133 MHz
1
2
3
Notes
Notes
:
1. Power measured does not include power dissipated in output drivers.
2. Typical power is an average value measured at 3.3 V in a system executing typical
applications and benchmark sequences. Typical power numbers should be used in planning
for proper thermal management.
3. Maximum power is measured at 3.3 V using a worst case instruction mix. These values should
be used for power supply design.
1.3 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 604. These specifications are for parts that
operate at processor core frequencies of 100, 120, and 133 MHz. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG0–PLL_CFG3 pins. All
timings are specified respective to the SYSCLK.
604 Hardware Specifications
Preliminary/Subject to Change without Notice
3
1.3.1 Clock AC Specifications
Table 5 provides the clock AC timing specifications as defined in Figure 1.
Table 5. PowerPC 604 Microprocessor Clock AC Timing Specifications
Vdd = 3.3
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105
°
C
100 MHz
Num
Characteristic
Min
Frequency of operation
Frequency of VCO
SYSCLK frequency
1
2,3
4
5
6
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle measured at 1.4 V
SYSCLK jitter
Internal PLL relock time
50
180
16.67
15.0
1.0
40
—
—
Max
100.0
360
66.67
60.0
2.0
60
±
150
100
Min
60.0
180
20.0
15.0
1.0
40
—
—
Max
120.0
360
66.67
50.0
2.0
60
±
150
100
Min
66.67
180
22.2
15.0
1.0
40
—
—
Max
133.3
360
66.67
45.0
2.0
60
±
150
100
MHz
MHz
MHz
ns
ns
%
ps
µ
s
5
6, 7
4
1
2
3
120 MHz
133 MHz
Unit
Notes
Notes
:
1. Times shown in specifications are only valid for the range of processor core frequencies specified.
2.
Caution
: The SYSCLK frequency and PLL_CFG0–PLL_CFG3 settings must be chosen such that the
resulting CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies.
3. AC timing specifications are tested up to the maximum SYSCLK (bus) frequency shown in Table 5.
However, it is theoretically possible to attain higher SYSCLK frequencies if allowed for by system design.
4. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
5. This number refers to cycle-to-cycle jitter.
6. PLL relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are
reached during the power-on reset sequence. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL relock time (100
µ
s) during the power-on reset sequence.
7. Relock timing is guaranteed by design and is not tested.
Figure 1 provides the SYSCLK input timing diagram.
1
4
2
CVih
SYSCLK
VM
CVil
VM = Midpoint Voltage (1.4 V)
Figure 1. SYSCLK Input Timing Diagram
3
4
Preliminary/Subject to Change without Notice
604 Hardware Specifications
1.3.2 Input AC Specifications
Table 6 provides the input AC timing specifications for the 604 as defined in Figure 2.
Table 6. PowerPC 604 Microprocessor Input AC Timing Specifications
Vdd = 3.3
±
5% V dc, GND = 0 V dc, 0
≤
T
j
≤
105
°
C
100 MHz
Num
Characteristic
Min
7
ARTRY, SHD, ABB, TS, XATS,
AACK,BG, DRTRY, TA, DBG, DBB, TEA,
DBDIS, and DBWO valid to SYSCLK
(setup)
All other inputs valid to SYSCLK (setup)
SYSCLK to all inputs invalid (hold)
Mode select input valid to HRESET (input
setup for DRTRY)
HRESET to mode select input invalid
(input hold for DRTRY)
5.5
Max
—
120 MHz
Min
5.0
Max
—
133 MHz
Unit
Min
5.0
Max
ns
Notes
8
9
10
11
5.5
0
8*
t
sysclk
0
—
—
—
—
4.0
0
8*
t
sysclk
0
—
—
—
—
4.0
0
8*
t
sysclk
0
—
—
—
—
ns
ns
ns
ns
1
1
2,3,4,5
2,3,4,5
Notes:
1. All other input signals include the following signals—all inputs except ARTRY, SHD, ABB, TS, XATS,
AACK, BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs.
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
3. t
sysclk
is the period of the external clock (SYSCLK) in nanoseconds.
4. These values are guaranteed by design, and are not tested.
5. Note this is for configuration of the fast-L2 mode. The DRTRY signal must be held negated during fast-L2
mode.
Figure 2 provides the input timing diagram for the 604.
VM
SYSCLK
7
8
9
ALL INPUTS
VM = Midpoint Voltage (1.4V)
Figure 2. PowerPC 604 Microprocessor Input Timing Diagram
604 Hardware Specifications
Preliminary/Subject to Change without Notice
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
