INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT238
3-to-8 line decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
FEATURES
•
Demultiplexing capability
•
Multiple input enable for easy expansion
•
Ideal for memory chip select decoding
•
Active HIGH mutually exclusive outputs
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A
0
, A
1
, A
2
) and when enabled,
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT238
provide 8 mutually exclusive active HIGH outputs
(Y
0
to Y
7
).
The “238” features three enable inputs: two active LOW
(E
1
and E
2
) and one active HIGH (E
3
). Every output will be
LOW unless E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
The “238” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The “238” is identical to the “138” but has non-inverting
outputs.
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
A
n
to Y
n
E
3
to Y
n
E
n
to Y
n
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
14
16
17
3.5
72
18
20
21
3.5
76
ns
ns
ns
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
PIN DESCRIPTION
PIN NO.
1, 2, 3
4, 5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
SYMBOL
A
0
to A
2
E
1
, E
2
E
3
GND
Y
0
to Y
7
V
CC
NAME AND FUNCTION
address inputs
enable inputs (active LOW)
enable input (active HIGH)
ground (0 V)
outputs (active HIGH)
positive supply voltage
74HC/HCT238
Fig.1 Pin configuration.
Fig.2 Logic symbol.
(a)
(b)
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
+25
min. typ.
t
PHL
/ t
PLH
propagation delay
A
n
to Y
n
propagation delay
E
3
to Y
n
propagation delay
E
n
to Y
n
output transition time
47
17
14
52
19
15
50
18
14
19
7
6
max.
150
30
26
160
32
27
155
31
26
75
15
13
−40
to
+85
min. max.
190
38
33
200
40
34
195
39
33
95
19
16
−40
to
+125
min.
max.
225
45
38
240
48
41
235
47
40
110
22
19
ns
74HC/HCT238
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Figs 6 and 7
December 1990
5
Embedded System
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