INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT594
8-bit shift register with output
register
Product specification
File under Integrated Circuits, IC06
December 1991
Philips Semiconductors
Product specification
8-bit shift register with output register
FEATURES
•
Synchronous serial input and output
•
8-bit parallel output
•
Shift and storage register have independent direct clear
and clocks
•
100 MHz (typ.)
•
Output capability:
– parallel outputs: bus driver
– serial outputs: standard
•
I
CC
category: MSI
APPLICATIONS
•
Serial-to parallel data conversion
•
Remote control holding register
DESCRIPTION
74HC/HCT594
The 74HC/HCT594 are high-speed, Si-gate CMOS
devices, and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC/HCT594 contain an 8-bit, non-inverting,
serial-in, parallel-out shift register that feeds an 8-bit
D-type storage register. Separate clocks and direct
overriding clears are provided on both the shift and storage
registers. A serial output (Q
7
’) is provided for cascading
purposes.
Both the shift and storage register clocks are positive-edge
triggered. If the user wishes to connect both clocks
together, the shift register will always be one count pulse
ahead of the storage register.
QUICK REFERENCE DATA
GND = 0 V: T
amb
= 250 C; t
r
= t
f
= 6 ns.
TYPICAL
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
SH
CP
to Q
7
’
ST
CP
to Q
n
SH
R
to Q
n
ST
R
to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
), where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of the outputs;
C
L
= output load capacitance in pF; V
CC
= supply voltage in V.
2. For HC, the condition is V
I
= GND to V
CC
; for HCT, the condition is V
I
= GND to V
CC
−
1.5 V.
ORDERING INFORMATION
PACKAGES
EXTENDED TYPE NUMBER
PINS
PC74HC/HCT594P
PC74HC/HCT594T
16
16
PIN POSITION
DIL
SO
MATERIAL
plastic
plastic
CODE
SOT38C, P
SOT109A
maximum clock frequency SH
CP
, ST
CP
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
13
13
11
11
100
3.5
84
15
15
14
14
100
3.5
89
ns
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1991
2
Philips Semiconductors
Product specification
8-bit shift register with output register
PINNING
SYMBOL
Q
0
to Q
7
GND
Q
7
’
SH
R
SH
CP
ST
CP
ST
R
D
s
V
CC
8
9
10
11
12
13
14
16
PIN
15 & 1 to 7
parallel data outputs
ground (0 V)
serial data output
shift register reset (active LOW)
shift register clock input
storage register clock input
storage register reset active (LOW)
serial data input
supply voltage
DESCRIPTION
74HC/HCT594
11
ge
12
ge
halfpage
SH CP ST CP
Q7'
Q0
Q1
Q2
14
DS
Q3
Q4
Q5
Q6
SH R
10
Q7
ST R
13
ST R
Q1 1
Q2 2
Q3 3
Q4 4
Q5 5
Q6 6
Q7
7
16 V CC
15 Q 0
14 D S
13 ST R
ST CP
13
12
10
R 1 SRG8
C1/
1D
R2
C2
9
15
1
2
3
4
5
6
7
SH R
11
SH CP
D S 14
2D
594
12 ST CP
11 SH CP
10 SH R
9
Q7'
GND 8
MBC318
15 Q
0
1
Q1
2
Q2
3
Q3
4
Q4
5
Q5
6
Q6
7
Q7
9
Q7'
MBC319
MBC322 - 1
Fig.1 Logic symbol.
Fig.2 Pin configuration.
Fig.3 IEC logic symbol.
December 1991
3
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, halfpage
14 D S
11
SHCP
8-STAGE SHIFT REGISTER
Q7'
12
ST CP
8-BIT STORAGE REGISTER
10 SH R
9
13 ST R
Q 0 Q1 Q 2 Q 3 Q4 Q 5 Q 6 Q 7
15
1
2
3
4
5
6
7
MBC320
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
SH
CP
X
X
X
↑
ST
CP
X
X
↑
X
SH
R
L
X
L
H
ST
R
X
L
H
X
X
X
X
H
D
S
OUTPUTS
FUNCTION
Q
7
’
L
NC
L
Q
6
’
Q
n
NC
L
L
NC
a LOW level on SH
R
only affects the shift registers.
a LOW level on ST
R
only affects the storage registers.
empty shift register loaded into storage register.
logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage
6 (internal Q
6
’) appears on the serial output (Q
7
’).
contents of shift register stages (internal Q
n
’) are transferred to
the storage register and parallel output stages.
contents of shift register shifted through. Previous contents of
shift register transferred to the storage register and the parallel
output stages.
X
↑
↑
↑
H
H
H
H
X
X
NC
Q
6
n
Q
n
’
Q
n
’
Note
1. H = HIGH voltage level
L = LOW voltage level
↑
= LOW-to-HIGH transition
NC = no change
X = don’t care.
December 1991
4
DSP and ARM Processors
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