Advance Information
MPC8255EC/D
Rev. 0.4, 5/2002
MPC8255
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC8255 PowerQUICC II™
communications processor.
The following topics are addressed:
Topic
Section 1.1, “Features”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.2.1, “DC Electrical Characteristics”
Section 1.2.2, “Thermal Characteristics”
Section 1.2.3, “Power Considerations”
Section 1.2.4, “AC Electrical Characteristics”
Section 1.3, “Clock Configuration Modes”
Section 1.3.1, “Local Bus Mode”
Section 1.4, “Pinout”
Section 1.5, “Package Description”
Section 1.6, “Ordering Information”
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2
5
5
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9
10
16
16
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Figure 1 shows the block diagram for the MPC8255.
16 Kbytes
I-Cache
I-MMU
G2 Core
System Interface Unit
(SIU)
16 Kbytes
D-Cache
D-MMU
Bus Interface Unit
60x-to-Local
Bridge
Memory Controller
Communication Processor Module (CPM)
Clock Counter
Timers
Parallel I/O
Baud Rate
Generators
32-bit RISC Microcontroller
and Program ROM
4 Virtual
IDMAs
Interrupt
Controller
32 Kbytes
Dual-Port RAM
Serial
DMAs
System Functions
60x Bus
Local Bus
32 bits, up to 83 MHz
MCC2
FCC1
FCC2
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
Time Slot Assigner
Serial Interface
4 TDM Ports
2 MII
Ports
2 UTOPIA
Ports
Non-Multiplexed
I/O
Figure 1. MPC8255 Block Diagram
1.1
•
•
Features
Footprint-compatible with the MPC8260
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–200 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
The major features of the MPC8255 are as follows:
2
MPC8255 Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
•
•
•
•
•
Separate power supply for internal logic (2.5 V in HiP3, 2.0 V in HiP4) and for I/O (3.3V)
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
•
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
•
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
MOTOROLA
MPC8255 Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
— Two fast communications controllers (FCC1 and FCC2) supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— One multichannel controller (MCC2)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
2
C) controller (identical to the MPC860 I
2
C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to four TDM interfaces
– Supports one group of four TDM channels
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
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MPC8255 Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Electrical and Thermal Characteristics
1.2
1.2.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8255.
This section describes the DC electrical characteristics for the MPC8255. Table 1 shows the maximum
electrical ratings.
Table 1. Absolute Maximum Ratings
1
Rating
Core supply voltage
2
PLL supply voltage
2
I/O supply voltage
3
Input voltage
4
Junction temperature
Storage temperature range
1
Symbol
VDD
VCCSYN
VDDH
VIN
T
j
T
STG
Value
-0.3 – 2.5
-0.3 – 2.5
-0.3 – 4.0
GND(-0.3) – 3.6
120
(-55) – (+150)
Unit
V
V
V
V
°C
°C
Absolute maximum ratings are stress ratings only; functional operation (see
Table 2) at the maximums is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage.
2
Caution:
VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time,
including during power-on reset.
3
Caution:
VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no
more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than
2.5 V during normal operation.
4
Caution:
VIN must not exceed VDDH by more than 2.5 V at any time, including
during power-on reset.
Table 2 lists recommended operational voltage conditions.
Table 2. Recommended Operating Conditions
1
Rating
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
Junction temperature (maximum)
Ambient temperature
1
Symbol
VDD
VCCSYN
VDDH
VIN
T
j
T
A
Value
1.7 – 2.1
2
/ 1.9–2.1
3
1.7 – 2.1
2
/ 1.9–2.1
3
3.135 – 3.465
GND (-0.3) – 3.465
105
4
0–70
4
Unit
V
V
V
V
°C
°C
Caution:
These are the recommended and tested operating conditions. Proper device
operating outside of these conditions is not guaranteed.
2
For devices operating at less than 233 MHz CPU, 166 MHz CPM, and 66 MHz bus
frequencies.
3
For devices operating at greater than or equal to 233 MHz CPU, 166 MHz CPM, and
66 MHz bus frequencies.
4
Note that for extended temperature parts the range is (-40) – 105 .
T
Tj
A
MOTOROLA
MPC8255 Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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