Philips Semiconductors
Product specification
2.9-Mbit field memory
FEATURES
•
2949264-bit field memory
•
245772
×
12-bit organization
•
3.3 V power supply
•
Inputs fully TTL compatible when using an extra 5 V
power supply
•
High speed read and write operations
•
FIFO operations:
– full word continuous read and write
– independent read and write pointers (asynchronous
read and write access)
– resettable read and write pointers
•
Optional random access by block function (40 words per
block) enabled during pointer reset operation
•
Quasi static (internal self-refresh and clocking pauses of
infinite length)
•
Write mask function
•
Cascade operation possible
•
16 Mbit CMOS DRAM process technology.
GENERAL DESCRIPTION
The SAA4955 is a 2949264-bit field memory designed for
advanced TV applications such as 100/120 Hz TV,
PALplus, PIP and 3D comb filter.
QUICK REFERENCE DATA
SYMBOL
T
cy(SWCK)
T
cy(SRCK)
t
ACC
V
DD
, V
DD(O)
V
DD(P)
I
DD(tot)
PARAMETER
WRITE cycle time (SWCK)
READ cycle time (SRCK)
READ access time after SRCK
supply voltage
supply voltage
total supply current
(I
DD(tot)
= I
DD
+ I
DD(O)
+ I
DD(P)
)
minimum read/write cycle;
outputs open
CONDITIONS
see Fig.4
see Fig.11
see Fig.11
MIN.
26
26
−
3.0
3.0
−
TYP.
−
−
−
3.3
3.3
22
SAA4955
The maximum storage depth is 245772 words
×
12 bits.
A FIFO operation with full word continuous read and write
could be used as a data delay, for example. A FIFO
operation with asynchronous read and write could be used
as a data rate multiplier. Here the data is written once, then
read as many times as required without being overwritten
by new data. In addition to the FIFO operations, a random
block access mode is accessible during the pointer reset
operation. When this mode is enabled, reading and/or
writing may begin at, or proceed from, the start address of
any of the 6144 blocks. Each block is 40 words in length.
Two or more SAA4955s can be cascaded to provide
greater storage depth or a longer delay, without the need
for additional circuitry.
The SAA4955 contains separate 12-bit wide serial ports
for reading and writing. The ports are controlled and
clocked separately, so asynchronous read and write
operations are supported. Independent read and write
clock rates are possible. Addressing is controlled by read
and write address pointers. Before a controlled write
operation can begin, the write pointer must be set to zero
or to the beginning of a valid address block. Likewise, the
read pointer must be set to zero or to the beginning of a
valid address block before a controlled read operation can
begin.
MAX.
−
−
21
3.6
5.5
70
UNIT
ns
ns
ns
V
V
mA
ORDERING INFORMATION
TYPE
NUMBER
SAA4955HL
SAA4955TJ
PACKAGE
NAME
LQFP44
SOJ40
DESCRIPTION
plastic low profile quad flat package; 44 leads; body 10
×
10
×
1.4 mm
plastic small outline package; 40 leads (J-bent); body width 10.16 mm
VERSION
SOT389-1
SOT449-1
2001 Jul 09
2
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