November 2003
rev 1.1
ASM3P2182A
LCD Panel EMI Reduction IC
Features
FCC approved method of EMI attenuation.
Provides up to 15dB EMI reduction.
Generates a 1X low EMI spread spectrum clock of
the input frequency.
Input frequency range: 25MHz to 210 MHz.
Internal loop filter minimizes external components
and board space.
Center spread.
4 spread frequency deviation selections: ± 0.13%
to ± 1.24%.
Low inherent cycle-to-cycle jitter.
3.3V operating voltage range.
TTL or CMOS compatible inputs and outputs.
Low power CMOS design.
Supports notebook VGA and other LCD timing
controller applications.
Products are available for industrial temperature
range.
Available in 8-pin SOIC and TSSOP.
The ASM3P2182A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
The ASM3P2182A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The ASM3P2182A reduces electromagnetic interference
(EMI) at the clock source, allowing system wide reduction
of EMI of
down stream clock and data dependent
signals. The ASM3P2182A allows significant system cost
savings by reducing the number of circuit board layers
ferrite beads, shielding and other passive components
that are traditionally required to pass EMI regulations.
Product Description
The ASM3P2182A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of input clock frequencies from 25MHz to 210MHz.
(Refer Input Frequency and Modulation Rate Table).
The
ASM3P2182A can generate an EMI reduced clock from
an OSC or a system generated clock. The ASM3P2182A
offers a Center Spread clock and with a percentage
deviation from ± 0.13% or ± 1.24%.
FS0
FS1
S0, S1
Applications
The ASM3P2182A is targeted towards EMI management
for memory and LVDS interfaces in mobile graphic
chipsets and high-speed digital applications such as PC
peripheral devices, consumer electronics, and embedded
controller systems.
VDD
Block Diagram
PLL
Modulation
XIN
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
VCO
Output
Divider
MODOUT
VSS
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM3P2182A
X2105A
Pin Configuration
XIN
GND
S1
S0
1
2
8
7
FS1
FS0
VDD
ModOUT
ASM3P2182A
3
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN
GND
S1
S0
MODOUT
VDD
FS0
FS1
Type
I
P
I
I
O
P
I
I
Description
Connect to externally generated clock signal.
Ground to entire chip.
Spread range select. Digital logic input used to select frequency deviation
(Refer
Spread Deviation Table).
This pin has an internal pull-up resistor.
Spread range select. Digital logic input used to select frequency deviation
(Refer
Spread Deviation Table).
This pin has an internal pull-up resistor.
Spread spectrum low EMI output.
Power supply for the entire chip (3.3V).
Frequency range select. Digital logic input used to select frequency range
(Refer
Input Frequency and Modulation Rate Table).
This pin has an internal
pull-up resistor.
Frequency range select. Digital logic input used to select frequency range
(Refer
Input Frequency and Modulation Rate Table).
This pin has an internal
pull-up resistor.
Input Frequency and Modulation Rate Table
FS1 (pin 8)
0
0
1
1
FS0 (pin 7)
0
1
0
1
Frequency Range
25MHz to 50MHz
50MHz to 103 MHz
75MHz to 150MHz
160MHz to 210MHz
Spread Deviation Selection Table
S1 (pin 3)
0
0
1
1
S0 (pin 4)
0
1
0
1
Spread Deviation (%)
± 0.13
± 0.41
± 0.66
± 1.24
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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ASM3P2182A
X2105A
Absolute Maximum Ratings
Symbol
VDD, VIN
TSTG
TA
Parameter
Voltage on any pin with respect to GND
Storage temperature
Operating temperature
Rating
-0.5 to + 7.0
-65 to +125
Unit
V
°C
0 to 70
°C
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
CC
I
DD
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Output low voltage (V
DD
= 3.3V, I
OL
= 20mA)
Output high voltage (V
DD
= 3.3V, I
OH
= 20mA)
Dynamic supply current
Normal mode (3.3V and 10pF loading)
Static supply current
Standby mode
Operating voltage
Power up time (first locked clock cycle after power up)
Clock out impedance
Parameter
Min
GND – 0.3
2.0
-
-
-
2.5
8.46
Typ
-
-
-
-
-
-
12
0.6
2.7
-
-
3.3
0.18
50
3.7
-
-
Max
0.8
V
DD
+ 0.3
-35
35
0.4
-
17.78
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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FPGA/CPLD
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