TSC80C51-40MXR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> TSC80C51-40MXR

TSC80C51-40MXR: DescriptionMicrocontroller, 8-Bit, MROM, 40MHz, CMOS, DIE; CategoryThe embedded processor and controller Microcontrollers and processors; File Size213KB，19 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

Download Datasheet Parametric View All

TSC80C51-40MXR Overview

Microcontroller, 8-Bit, MROM, 40MHz, CMOS, DIE

TSC80C51-40MXR Parametric

Parameter Name	Attribute value
package instruction	DIE
Reach Compliance Code	unknown
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	R-XUUC-N40
Number of I/O lines	32
Number of terminals	40
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
PWM channel	NO
Package body material	UNSPECIFIED
encapsulated code	DIE
Package shape	RECTANGULAR
Package form	UNCASED CHIP
Certification status	Not Qualified
ROM programmability	MROM
speed	40 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal location	UPPER
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

Preview

Download Datasheet

View All

TSC80C31/80C51

CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller

Description

The TSC80C31/80C51 is high performance SCMOS

versions of the 8051 NMOS single chip 8 bit

µC.

The fully static design of the TSC80C31/80C51 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TSC80C31/80C51 retains all the features of the 8051

: 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ;

two 16 bit timers ; a 5-source, 2-level interrupt structure

; a full duplex serial port ; and on-chip oscillator and clock

circuits.

In addition, the TSC80C31/80C51 has two

software-selectable modes of reduced activity for further

reduction in power consumption. In the Idle Mode the

CPU is frozen while the RAM, the timers, the serial port,

and the interrupt system continue to function. In the

Power Down Mode the RAM is saved and all other

functions are inoperative.

The TSC80C31/80C51 is manufactured using SCMOS

process which allows them to run from 0 up to 44 MHz

with VCC = 5 V. The TSC80C31/80C51 is also available

at 20 MHz with 2.7 V < Vcc < 5.5 V.

TSC80C31/80C51-L16 : Low power version

Vcc : 2.7–5.5 V Freq : 0–16 MHz

TSC80C31/80C51-L20 : Low power version

Vcc : 2.7–5.5 V Freq : 0–20 MHz

TSC80C31/80C51-12 : 0 to 12 MHz

TSC80C31/80C51-20 : 0 to 20 MHz

TSC80C31/80C51-25 : 0 to 25 MHz

TSC80C31/80C51-30 : 0 to 30 MHz

TSC80C31/80C51-36 : 0 to 36 MHz

TSC80C31/80C51-40 : 0 to 40 MHz

TSC80C31/80C51-44 : 0 to 44 MHz*

* Commercial and Industrial temperature range only. For other speed

and range please consult your sale office.

Features

Power control modes

128 bytes of RAM

4 K bytes of ROM (TSC80C31/80C51)

32 programmable I/O lines

Two 16 bit timer/counter

64 K program memory space

64 K data memory space

Fully static design

0.8

µm

CMOS process

Boolean processor

5 interrupt sources

Programmable serial port

Temperature range : commercial, industrial, automotive and

military

Optional

Secret ROM : Encryption

Secret TAG : Identification number

MATRA MHS

Rev. E (14 Jan.97)

Recommended Resources

Stage thyristor dimming circuit 2

LAS16U, LAS19U typical application circuit diagram

Cordless phone anti-theft circuit diagram

Tube amplifier CS8412+PCM63 classic design (power supply part) circuit diagram

Suopu SP-220 induction cooker circuit diagram

STK0025 power amplifier circuit

[FPGA entry to actual combat] Verilog state machine description style source code & Q&A: [FPGA entry to actual combat] ex_3: Verilog state machine description style, state machine structure with engineering value - originated from Huawei; Source code: If students do not understand the kno...; 尤老师 FPGA/CPLD

Newbie WindowsCE CImageList::DrawIndirect(...) cannot be connected: How to solve it?...; flyingzero Embedded System

Tomorrow is the beginning of winter~: Tomorrow is the beginning of winter. Winter is really here. Friends in the north are going to eat dumplings again. Guan Guan in the south is shivering and needs a hot pot to keep warm. Important thing...; okhxyyo Talking

An example of RDA where the pull method succeeds but the push method fails: //Submit data to the server void CRDAExamDlg::OnBtnpush() { ISSCERDA*pCERDA = NULL; BSTR bStr = NULL; BSTR bConnectStr = NULL; BSTR bLocalConnectStr = NULL; BSTR bLocalTableName = NULL; SYSTEMTIME sys...; stone3w Embedded System

Both DC and AC regulated output: DC can output a regulated voltage, but AC cannot output a regulated voltage. What is the reason? . ....; secondlife110 Analog electronics

Help: How to build a database: As the title says, I have a fully customized standard unit and I want to generate a .lib file. How can I do this? Can anyone tell me what tool to use? Thanks!...; porsche_ FPGA/CPLD

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components