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MIP7365-450F17M

Description
Microprocessor, 64-Bit, 450MHz, CMOS, CQFP208, 1.20 X 1.20 MM, CERAMIC, QFP-208
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size286KB,16 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

MIP7365-450F17M Overview

Microprocessor, 64-Bit, 450MHz, CMOS, CQFP208, 1.20 X 1.20 MM, CERAMIC, QFP-208

MIP7365-450F17M Parametric

Parameter NameAttribute value
Parts packaging codeQFP
package instructionQFP,
Contacts208
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Address bus width
bit size64
boundary scanYES
maximum clock frequency133 MHz
External data bus width
FormatFLOATING POINT
Integrated cacheYES
JESD-30 codeR-CQFP-G208
length28 mm
low power modeYES
Number of terminals208
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQFP
Package shapeRECTANGULAR
Package formFLATPACK
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height3.302 mm
speed450 MHz
Maximum supply voltage1.35 V
Minimum supply voltage1.25 V
Nominal supply voltage1.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formGULL WING
Terminal pitch1.1 mm
Terminal locationQUAD
width28 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR
Base Number Matches1
Standard Products
MIP7365
64-Bit Superscaler Microprocessor
January 11, 2007
FEATURES
Upscreened PMC-Sierra RM7065C
Military and Industrial Grades Available
Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level
price/performance
o 450MHz operating frequency
High-performance system interface
o Multiplexed address/data bus (SysAD) supports 2.5V, 3.3V I/O logic
o Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
o Support for 64-bit or 32-bit external agents
Integrated primary and secondary caches
o All are 4-way set associative with 32-byte line size
o 16-Kbytes instruction, 16-Kbytes data, 256-Kbytes on-chip secondary
o Per line cache locking in primaries and secondary
o Fast Packet Cache™ increases system efficiency in networking applications
High-performance floating-point unit — 1600MFLOPS maximum
o Single cycle repeat rate for common single-precision operations and some double-precision operations
o Single cycle repeat rate for single-precision combined multiply-add operations
o Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
MIPS IV superset instruction set architecture
o Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
o Single-cycle floating-point multiply-add
Integrated memory management unit
o Fully associative joint TLB (shared by I and D translations)
o 64/48 dual entries map 128/96 pages
o Variable page size
Embedded application enhancements
o Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply
instruction (MUL)
o I&D Test/Break-point (Watch) registers for emulation & debug
o Performance counter for system and software tuning & debug
o Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software
Fully static CMOS design with dynamic power down logic
216-EPad LQFP 24x24mm are pin compatible with the RM7965 and RM5261A EPad™ products
NOTE: 216-Enhanced Pad package, EPad MIPS64 and Fast Packet Cache are Trademarks of PMC-Sierra
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