74LS107A datasheet, PDF - EEWORLD Datasheet

74LS107A: DescriptionLS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14; Categorylogic logic; File Size33KB，1 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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74LS107A Overview

LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknown
series	LS
JESD-30 code	R-PDIP-T14
Load capacitance (CL)	15 pF
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	IN-LINE
Maximum supply current (ICC)	8 mA
propagation delay (tpd)	30 ns
Certification status	Not Qualified
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal form	THROUGH-HOLE
Terminal location	DUAL
Trigger type	NEGATIVE EDGE
minfmax	30 MHz
Base Number Matches	1

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