A32200XLV-VQB datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > A32200XLV-VQB

Preview

A32200XLV-VQB: DescriptionIntegrator Series FPGAs: 1200XL and 3200DX Families; File Size604KB，84 Pages; ManufacturerActel; Websitehttp://www.actel.com/

Download Datasheet View All

A32200XLV-VQB Overview

Integrator Series FPGAs: 1200XL and 3200DX Families

Preview

Download Datasheet

View All

Discontinued – v3.0

v3.0

Integrator Series FPGAs:

1200XL and 3200DX Families

F ea t u re s

H ig h C a p ac it y

G e n e ra l D es c ri p t i o n

•

2,500 to 30,000 Logic Gates

Up to 3Kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 250 User-Programmable I/O Pins

225 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

H ig h P e r f o r m a nc e

Actel’s Integrator Series FPGAs are the first programmable

logic devices optimized for high-speed system logic

integration. Based on Actel’s proprietary antifuse

technology and 0.6-micron double metal CMOS process,

Integrator Series devices offer a fine-grained, register-rich

architecture with embedded dual-port SRAM and

wide-decode circuitry.

Integrator Series’ 3200DX and 1200XL families were

designed to integrate system logic which is typically

implemented in multiple CPLDs, PALs, and FPGAs. These

devices provide the features and performance required for

today’s complex, high-speed digital logic systems. The

3200DX family offers fast dual-port SRAM for implementing

FIFOs, LIFOs, and temporary data storage. The large

number of storage elements can efficiently address

applications requiring wide datapath manipulation and

transformation functions such as telecommunications,

networking, and DSP.

E a s e - of -I n t e g r a t i o n

• Synthesis-Friendly Architecture Supports ASIC Design

Methodologies.

• 95–100% Device Utilization using Automatic

Place-and-Route Tools.

• Deterministic, User-Controllable Timing Via Timing

Driven Software Tools with Up To 100% Pin Fixing.

• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.

In t eg r a to r S e ri e s P ro d u ct P r of i l e F a m i l y

1200XL

Device

A1225XL

2,500

N/A

231

220

N/A

231

A1240XL

4,000

N/A

348

336

N/A

348

104

A1280XL

8,000

N/A

624

608

N/A

624

140

3200DX

A3265DX

6,500

N/A

510

475

N/A

510

126

PL84

PQ100

PQ160

TQ176

A32100DX

10,000

2,048

700

662

700

152

Yes

PL84

PQ160

PQ208

TQ176

CQ84

A32140DX

14,000

N/A

954

912

N/A

954

176

Yes

PL84

PQ160

PQ208

TQ176

CQ256

A32200DX

20,000

2,560

1,230

1,184

1,230

202

Yes

PQ208

RQ208

RQ240

CQ208

CQ256

A32300DX

30,000

3,072

1,888

1,833

1,888

250

Yes

RQ208

RQ240

CQ256

Capacity

Logic Gates

SRAM Bits

Sequential

Combinatorial

Decode

Logic Modules

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Clocks

User I/O

(Maximum)

JTAG

Packages

PL84

PQ100

VQ100

PG100

PL84 PQ100

PQ144

TQ176

PG132

PL84

PQ160 PQ208

TQ176

PG176 CQ172

Note:

Logic gate capacity does not include SRAM bits as logic.

February 2001

Recommended Resources

Harmonic current phase failure protection circuit 3b

Multifunctional motor protection circuit

Sanhe DAF-98B fully automatic electronic drinking fountain circuit diagram

Precision current source circuit diagram using AD586

TA7688P power amplifier circuit

water level meter circuit

Embedded Problems: The topic is as follows: Design an embedded system for a specific application. Requirements: 1. Have a complete system design plan 2. Have a complete description of the system plan 3. Have a correspon...; weiaa1911 Embedded System

The chips sent by TI seminar arrived by express delivery, but all other chips except 430 are unusable!: The chip samples given at the TI seminar were sent by FedEx at an incredibly fast speed from Shanghai to Beijing. Except for the 430 chip, the rest were BGA packages and could not be used. They could ...; o0pingu0o Microcontroller MCU

Newcomer food problem: How to remove EEPROM data in .hex file? Thanks in advance. Note: Use PIC 150K to write PIC16F628A. The programmer cannot pre-write EEPROM. Remove EEPROM data in Hex file....; kieferyu Microchip MCU

How to design and implement dual network card hot backup (dual network card redundant backup) (2)?: Hello? Under WIN2000, Ethernet network, dual network card hot backup, that is, if one network card is broken, the other redundant network card will hot switch, and the two network cards have the same ...; laopo163 Embedded System

EEWORLD University Hall----CES 2015 Focus: Smart Digital Photo Frame CEIVA: CES 2015 Focus: Smart Digital Photo Frame CEIVA : https://training.eeworld.com.cn/course/242CEIVA豈是只一般数码相框?-?是世界首个连线的数码相框。于CES的Atmel展位展出。...; dongcuipin Talking

Have you ever used a gym membership card?: Today, I heard people around me talking about gym memberships, and I thought of looking for gym memberships a week ago. Jinqiu’s Haosha is said to be crowded except in the morning; Walmart’s Bluebird ...; 绿茶 Talking

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components