Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute
maximum ratings for extended periods may affect device reliability. Operating ranges define those limits between which the functionality of the device is guaranteed.
Electrical Characteristics
VCC = 4.5V to 5.5V, T
A
= Operating Temperature Range, unless otherwise noted.
Parameter
Supply Voltage Range
Supply Current
ST and PBRST Input Levels
Input Leakage
Output Source Current, RST
Output Sink Current, RST, RST
VCC 5% Trip Point (Reset
Threshold Voltage)
VCC 10% Trip Point (Reset
Threshold Voltage)
Input Capacitance, ST, TOL
Output Capacitance, RST, RST
Conditions
VCC
ICC (See Note 1)
VIH (See Note 2)
VIL
IIL
VOH = 2.4V
VOL = 0.4V
TOL = Gnd
TOL = VCC
CIN (See Note 3)
COUT (See Note 3)
1.0
2.0
4.50
4.25
10
10
4.62
4.37
4.74
4.49
5
7
2.0
-0.3
Min
4.5
18
Typ
Max
5.5
40
VCC +0.3
0.8
±1
Units
V
µA
V
µA
mA
mA
V
V
pF
pF
2
MIC1232
µP
Supervisory Circuit
A.C. Electrical Characteristics
VCC = 4.5V to 5.5V, T
A
= Operating Temperature Range, unless otherwise noted.
Parameter
PBRST Min. Pulse Width, tPB
PBRST Delay, tPBD
Reset Active Time, tRST
ST Pulse Width, tST
ST Timeout Period, tTD
TD = 0V
TD = Open
TD = VCC
Conditions
PBRST = VIL (see note 4)
Min
20
1
250
20
62.5
250
500
10
0
VCC Falling (see note 5)
VCC Rising (see note 6)
250
50
150
150
600
1200
250
1000
2000
4
610
20
1000
Typ
Max
Units
ms
ms
ms
ns
ms
VCC Fall Time, tF
VCC Rise Time, tR
VCC Detect to RST Low
and RST High, tRPD
VCC Detect to RST Open
and RST Low, tRPU
Note
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
6:
µs
ns
µs
ms
610
1000
ICC is measured with outputs open and inputs within 0.5V of supply rails.
PBRST has an internal pull-up resistor to VCC (typ. 40kΩ).
Guaranteed by design.
PBRST must be held low for a minimum of 20ms to guarantee a reset.
VCC falling at 1.66mv/µs.
RST has an open drain output.
3
MIC1232
µP
Supervisory Circuit
Pin Functions
Pin 1:
PBRST
- Pushbutton reset input. This input is debounced and can be driven with external logic signals or by
means of a mechanical pushbutton to actively force a reset. All pulses less than 1ms in duration on the
PBRST pin are ignored, whereas, any pulse with a duration of 20ms or greater is guaranteed to cause a
reset.
Pin 2:
TD
- Time delay input. This input selects the timebase used by the watchdog timer. When TD = 0V, the
watchdog timeout period is set to a nominal value of 150ms, when TD = open, the watchdog timeout period is
set to a nominal value of 600ms and when TD = VCC, the watchdog timeout period is 1.2sec nominally.
Pin 3:
TOL
- Tolerance select input. Selects whether 5% or 10% of VCC is used as the reset threshold voltage.
When TOL = 0V, the 5% tolerance level is selected and when TOL = VCC, a 10% tolerance level is selected.
Pin 4:
GND
- IC ground pin, 0V reference.
Pin 5:
RST
- RST is asserted high if either VCC goes below the reset threshold, the watchdog times out or PBRST is
pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the
reset threshold or after the watchdog times out or after PBRST goes high.
Pin 6:
RST
- RST is asserted low if either VCC goes below the reset threshold, the watchdog times out or PBRST is
pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period after VCC exceeds the
reset threshold or after the watchdog times out or after PBRST goes high. Open-drain output.
Pin 7:
ST
- Input to the watchdog timer. If ST does not see a transition from high to low within the watchdog timeout
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MCU
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