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SYS8512FKI-35

Description
SRAM Module, 512KX8, 35ns, CMOS, PDIP32, PLASTIC, DIP-32
Categorystorage    storage   
File Size109KB,7 Pages
ManufacturerMOSAIC
Websitehttp://www.mosaicsemi.com/
Download Datasheet Parametric View All

SYS8512FKI-35 Overview

SRAM Module, 512KX8, 35ns, CMOS, PDIP32, PLASTIC, DIP-32

SYS8512FKI-35 Parametric

Parameter NameAttribute value
Parts packaging codeDIP
package instruction,
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time35 ns
JESD-30 codeR-PDIP-T32
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX8
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal locationDUAL
Base Number Matches1
512K x 8 SRAM MODULE
SYS8512FK-20/25/35/45
Issue 5.0 : November 1999
Features
Access Times of 20/25/35/45 ns.
32 Pin 0.6" Dual-In-Line package with
JEDEC compatible pinout.
5 Volt Supply ± 10%.
Low Power Dissipation:
Average (min cycle)
2.42W (maximum).
Standby -L (CMOS)
44mW (maximum).
Completely Static Operation.
Equal Access and Cycle Times.
All Inputs and Outputs Directly TTL Compatible
On-board Supply Decoupling Capacitors.
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Description
The SYS8512FK is plastic 4M Static RAM Module
housed in a standard 32 pin Dual-In-Line package
organised as 512K x 8. The module utilises fast
256Kx4 SRAMs housed in SOJ packages, and
uses double sided surface mount techniques to
achieve a very high density module.
The module has Chip Select, Write Enable and
Output Enable control inputs; the Output Enable
pin allows faster access times than address access
during a Read Cycle.
Block Diagram
A0 - A17
D0 - D7
WE
OE
Pin Definition
256K X 4
SRAM
CS
256K X 4
SRAM
CS
256K X 4
SRAM
CS
256K X 4
SRAM
CS
CS
A18
DECODER
Pin Functions
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power (+5V)
Ground
A0 - A18
D0 - D7
CS
WE
OE
V
CC
GND
Package Details
Plastic 32 pin 0.6" Jedec DIP
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