SN74LS377
Octal D Flip-Flop
with Enable
The SN74LS377 is an 8-bit register built using advanced Low
Power Schottky technology. This register consists of eight D-type
flip-flops with a buffered common clock and a buffered common
clock enable.
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•
•
•
•
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8-Bit High Speed Parallel Registers
Positive Edge-Triggered D-Type Flip Flops
Fully Buffered Common Clock and Enable Inputs
True and Complement Outputs
Input Clamp Diodes Limit High Speed Termination Effects
LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
20
1
PLASTIC
N SUFFIX
CASE 738
20
1
SOIC
DW SUFFIX
CASE 751D
ORDERING INFORMATION
Device
SN74LS377N
SN74LS377DW
Package
16 Pin DIP
16 Pin
Shipping
1440 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS377/D
SN74LS377
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
20
Q
7
19
D
7
18
D
6
17
Q
6
16
Q
5
15
D
5
14
D
4
13
Q
4
12
CP
11
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
E
2
Q
0
3
D
0
4
D
1
5
Q
1
6
Q
2
7
D
2
8
D
3
9
Q
3
10
GND
LOADING
(Note a)
PIN NAMES
E
D
0
– D
3
CP
Q
0
– Q
3
Q
0
– Q
3
Enable (Active LOW) Input
Data Inputs
Clock (Active HIGH Going Edge) Input
True Outputs
Complemented Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
D
0
E
ENABLE
1
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
CLOCK
11
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
Q
0
2
Q
1
5
Q
2
6
Q
3
9
Q
4
12
Q
5
15
Q
6
16
Q
7
19
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2
SN74LS377
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
Input HIGH Current
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
0.5
20
0.1
– 0.4
– 100
28
V
µA
mA
mA
mA
mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
I
IH
I
IL
I
OS
I
CC
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, I
CC
is measured after a momentary GND, then 4.5 V is applied to clock.
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
f
MAX
t
PLH
t
PHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Min
30
Typ
40
17
18
27
27
Max
Unit
MHz
ns
Test Conditions
V
CC
= 5 0 V
5.0
C
L
= 15 pF
AC SETUP REQUIREMENTS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
W
t
s
t
s
t
h
Parameter
Any Pulse Width
Data Setup Time
Enable Setup
Time
Any Hold Time
Inactive — State
Active — State
Min
20
20
10
25
5.0
Typ
Max
Unit
ns
ns
ns
ns
ns
V
CC
= 5.0 V
Test Conditions
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
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3
SN74LS377
TRUTH TABLE
E
H
L
L
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
CP
D
n
X
H
L
Q
n
No
Change
H
L
Q
n
No
Change
L
H
AC WAVEFORM
1/f
max
CP
1.3 V
t
s(H)
D OR E
*
1.3 V
t
PLH
Q
1.3 V
t
s(L)
t
h(H)
t
W
1.3 V
t
h(L)
1.3 V
t
PHL
1.3 V
*The shaded areas indicate when the input is permitted to
change for predictable output performance.
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4
SN74LS377
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0
_
15
_
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0
_
15
_
0.51
1.01
B
1
10
C
L
–T–
SEATING
PLANE
K
M
E
G
F
D
20 PL
N
J
0.25 (0.010)
M
20 PL
0.25 (0.010)
T A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
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