MC88915TFN70 datasheet, PDF - EEWORLD Datasheet

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MC88915TFN70: DescriptionPLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28; Categorylogic logic; File Size217KB，20 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC88915TFN70 Overview

PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28

MC88915TFN70 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	QCCJ,
Reach Compliance Code	unknown
Other features	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F
series	88915
Input adjustment	MUX
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.505 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Number of functions	1
Number of inverted outputs	1
Number of terminals	28
Actual output times	7
Maximum operating temperature	70 °C
Minimum operating temperature
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.75 ns
Maximum seat height	4.57 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	11.505 mm
minfmax	70 MHz
Base Number Matches	1

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC88915TFN55

MC88915TFN70

MC88915TFN100

MC88915TFN133

MC88915TFN160

Low Skew CMOS PLL

Clock Drivers, 3-State

55, 70, 100, 133 and 160MHz Versions

The MC88915T Clock Driver utilizes phase–locked loop technology to

lock its low skew outputs’ frequency and phase onto an input reference

clock. It is designed to provide clock distribution for high performance

PC’s and workstations. For a 3.3V version, see the MC88LV915T data

sheet.

The PLL allows the high current, low skew outputs to lock onto a single

clock input and distribute it with essentially zero delay to multiple

components on a board. The PLL also allows the MC88915T to multiply a

low frequency input clock and distribute it locally at a higher (2X) system

frequency. Multiple 88915’s can lock onto a single reference clock, which

is ideal for applications when a central system clock must be distributed

synchronously to multiple boards (see Figure 7).

LOW SKEW CMOS

PLL CLOCK DRIVER

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°

phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”

frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail

the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the

“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1

and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on

page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding

FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915

in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board

test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see detailed

description on page 11).

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the

OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC

input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.

A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go

low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a

SYNC signal and full 5V VCC.

Features

•

Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

•

The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD

specification, which defines the part–to–part skew)

•

Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

•

Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)

•

Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available

•

All outputs have

±36

mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs

are TTL–level compatible.

±88mA

IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge

All outputs can go into high impedance (3–state) for board test purposes

•

Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

•

Lock Indicator (LOCK) accuracy indicates a phase–locked state

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

1/97

Motorola, Inc. 1997

REV 4

MC88915TFN70 Related Products

	MC88915TFN70	MC88915TFN133
Description	PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28	PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28
Is it Rohs certified?	incompatible	incompatible
package instruction	QCCJ,	QCCJ,
Reach Compliance Code	unknown	unknown
Other features	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F
series	88915	88915
Input adjustment	MUX	MUX
JESD-30 code	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	e0
length	11.505 mm	11.505 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Number of functions	1	1
Number of inverted outputs	1	1
Number of terminals	28	28
Actual output times	7	7
Maximum operating temperature	70 °C	85 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.75 ns	0.75 ns
Maximum seat height	4.57 mm	4.57 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD
width	11.505 mm	11.505 mm
minfmax	70 MHz	133 MHz
Base Number Matches	1	1

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