ISO 7816 Compatible
64K
X76F641
Secure SerialFlash
DESCRIPTION
8K x 8 + 32 x 8
FEATURES
• 64-bit password security
—Five 64-bit passwords for read, program and
reset
• 8192 byte+32 byte password protected arrays
—Separate read passwords
—Separate write passwords
—Reset password
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of both arrays
—Password protected reset
• 32-bit response to reset (RST input)
• 32 byte sector program
• 400kHz clock rate
• 2-wire serial interface
• Low power CMOS
—2.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
—8-lead EIAJ SOIC
—SmartCard module
BLOCK DIAGRAM
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Data Transfer
Array Access
Enable
8K Byte
SerialFlash Array
Array 0
(Password Protected)
Password Array
and Password
Verification Logic
32 Byte
SerialFlash Array
Array 1
(Password Protected)
Reset
Response Register
Retry Counter
SCL
SDA
O
Interface
Logic
RST
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P
ro
The X76F641 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
The X76F641 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F641 utilizes Xicor’s proprietary Direct Write
™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
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The X76F641 is a Password Access Security Supervi-
sor, containing one 65536-bit Secure SerialFlash array
and one 256-bit Secure SerialFlash array. Access to
each memory array is controlled by five 64-bit pass-
words each. These passwords protect read and write
operations of the memory array. A separate RESET
password is used to reset the passwords and clear the
memory arrays in the event the read and write pass-
words are lost.
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Characteristics subject to change without notice.
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X76F641
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a true three state serial data input/output pin.
During a read cycle, data is shifted out on this pin. Dur-
ing a write cycle, data is shifted in on this pin. In all
other cases, this pin is in a high impedance state.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
the X76F641 will output 32 bits of fixed data, which
conforms to the standard for “synchronous response to
reset”. The part must not be in a write cycle for the
response to reset to occur. See Figure 11. If there is
power interrupted during the Response to Reset, the
response to reset will be aborted and the part will
return to the standby state. The response to reset is
“mask programmable” only!
DEVICE OPERATION
There are two primary modes of operation for the
X76F641; protected READ and protected WRITE. Pro-
tected operations must be performed with one of four
8-byte passwords.
If the X76F641 is in a nonvolatile write cycle a “no
ACK” (SDA = High) response will be issued in
response to loading of the command byte. If a stop is
issued prior to the nonvolatile write cycle, the write
operation will be terminated and the part will reset and
enter into standby mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
SDA
SCL
RST
V
CC
V
SS
NC
P
ro
EIAJ SOIC
V
SS
NC
SDA
NC
1
2
3
4
8
7
6
5
PIN CONFIGURATION
Smart Card
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The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge Polling.) The data transfer
can occur only after the correct password is accepted
and an ACK polling has been performed.
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Serial Clock Input
Reset Input
Ground
Supply Voltage
No Connect
V
CC
RST
SCL
NC
SCL
NC
Description
Serial Data Input/Output
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To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
After each transaction is completed, the X76F641 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
REV 1.0 7/5/00
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Characteristics subject to change without notice.
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V
CC
RST
GND
NC
SDA
NC
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X76F641
Figure 1. X76F641 Device Operation
Load Command Byte
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
Start Condition
Load 2 Byte Address
Read/Write
Data Bytes
Two or Data ACK Polling
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Retry Counter
The X76F641 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, all memory areas are cleared
and the device is locked, thereby preventing any read
or write array password matches. The passwords are
unaffected. If a correct password is received prior to
retry counter overflow, the retry counter is reset and
access is granted. In order to reset the operation of a
locked up device, a special reset command must be
used with a RESET password.
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Device Protocol
The X76F641 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F641 will be considered a
slave in all applications.
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Stop Condition
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F641 will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If both
the device and a write condition have been selected, the
X76F641 will respond with an acknowledge after the
receipt of each subsequent eight-bit word.
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Verify Password
Acceptance by
Use of Password ACK Polling
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F641 continuously monitors the SDA
and SCL lines for the start condition, and will not
respond to any command until this condition is met.
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Characteristics subject to change without notice.
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Load 8-Byte
Password
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X76F641
Reset Device Command
The reset device command is used to clear the retry
counter and reactivate the device. When the reset
device command is used prior to the retry counter
overflow, the retry counter is reset and no arrays or
passwords are affected. If the retry counter has over-
flowed, all memory areas are cleared and all com-
mands are blocked and the retry counter is disabled.
Figure 2. Data Validity
Issuing a valid reset device command (with reset pass-
word) to the device resets and re-enables the retry
counter and re-enables the other commands. Again,
the passwords are not affected.
SCL
SDA
Data Stable
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
START Condition
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STOP Condition
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Data
Change
Characteristics subject to change without notice.
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Reset Password Command
A reset password command will clear both arrays and
set all passwords to all zero.
X76F641
Table 1. X76F641 Instruction Set
1
st
Byte 1
st
Byte After
After Start
Password
1000 0000
1000 1000
1001 0000
1001 1000
1010 0000
1010 1000
1011 0000
1011 1000
1100 0000
1110 0000
1110 1000
1111 0000
High Address
High Address
High Address
High Address
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
not used
not used
All the rest
Note:
2
nd
Byte After
Password
Low address
Low address
Low address
Low address
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
not used
not used
Command Description
Read (Array 0)
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
Password
Used
Read 0
Read 1
Write 0
Write 1
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ACK
Wait t
WC
OR
Repeated
ACK Polling
Command
Data 0
ACK
STOP
Wait t
WC
S Data ACK Polling
ACK
ACK
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Reserved
Write
Password
0
ACK
ACK
ACK
ACK
A7
A6
A5
A4
A3
A2
A1
A0
Data 31
Reset Password command
Reset Device command
ACK Polling command (Ends password operation)
Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
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Figure 4. Sector Programming
START
Command
bs
SDA S
O
START
ACK Polling
Command
S
NACK
ACK
A15
A14
A13
A12
A11
A10
A9
A8
If ACK, then
Password Matches
ACK
et
Sector Programming
The sector program mode requires issuing the 8-bit
write command followed by the password, the pass-
word ACK command, the address and then the data
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PROGRAM OPERATIONS
bytes transferred as illustrated in Figure 4. Up to 32
bytes may be transferred. After the last byte to be
transferred is acknowledged, a stop condition is
issued, which starts the nonvolatile write cycle.
Write
Password
7
REV 1.0 7/5/00
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Characteristics subject to change without notice.
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Read 0
Read 1
Write 0
Write 1
Reset
Reset
Reset
None
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