INTEGRATED CIRCUITS
74LV4094
8-stage shift-and-store bus register
Product specification
1998 Jun 23
Philips
Semiconductors
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
FEATURES
•
Optimized for low voltage applications: 1.0 to 3.6 V
•
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
•
Typical V
OLP
(output ground bounce) < 0.8 V at V
CC
= 3.3 V,
•
Typical V
OHV
(output V
OH
undershoot) > 2 V at V
CC
= 3.3 V,
•
Output capability: standard
•
I
CC
category: MSI
Applications:
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT4094.
The 74LV4094 is an 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input (D) to the parallel buffered 3-State outputs (QP
0
to OP
7
). The
parallel outputs may be connected directly to the common bus lines.
Data is shifted on the positive-going clock (CP) transitions. The data
in each shift register is transferred to the storage register when the
strobe input (STR) is HIGH. Data in the storage register appears at
the outputs whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS
1
and QS
2
) are available for cascading a
number of 74LV4094 devices. Data is available at QS
1
on the
positive-going clock edges to allow high-speed operation in
cascaded systems in which the clock rise time is fast. The same
serial information is available at QS
2
on the next negative going
clock edge and is for cascading 74LV4094 devices when the clock
rise time is slow.
•
Serial-to-parallel data conversion
•
Remote control holding register
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
=t
f
≤
2.5 ns
SYMBOL
PARAMETER
Propagation delay
CP to QS
1
CP to QS
2
CP to QP
n
STR to QP
n
Maximum clock frequency
Input capacitance
Power dissipation capacitance per gate
CONDITIONS
C
L
= 15 pF;
V
CC
= 3.3 V
TYPICAL
14
13
18
17
95
3.5
UNIT
t
PHL
/t
PLH
ns
f
MAX
C
I
C
PD
MHz
pF
pF
V
CC
= 3.3 V
V
I
= GND to V
CCNO TAG
83
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic DIL
16-Pin Plastic SO
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV4094 N
74LV4094 D
NORTH AMERICA
74LV4094 N
74LV4094 D
PKG. DWG. #
SOT38-4
SOT109-1
PIN CONFIGURATION
STR
D
CP
QP
0
QP
1
QP
2
QP
3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OE
QP
4
QP
5
QP
6
QP
7
QS
2
QS
1
PIN DESCRIPTION
PIN NUMBER
1
2
3
4, 5, 6, 7, 14,
13, 12, 11
8
9, 10
15
16
SYMBOL
STR
D
CP
QP
0
to QP
7
GND
QS
1
, QS
2
OE
V
CC
FUNCTION
Strobe input
Serial input
Clock input
Parallel outputs
Ground (0 V)
Serial outputs
Output enable input
Positive supply voltage
SV01611
1998 Jun 23
2
853-2078 19619
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
LOGIC SYMBOL
3
1
LOGIC SYMBOL (IEEE/IEC)
1
15
CP
STR
QS
1
QS
2
QP
0
QP
1
9
SRG8
10
4
5
6
7
7
QP
4
QP
5
QP
6
QP
7
OE
14
14
13
12
12
11
11
9
15
13
2
1D
2D
3
4
5
6
QP
3
3
C1/
C2
EN3
2
QP
2
D
SV01612
10
FUNCTIONAL DIAGRAM
D
CP
SV01613
2
3
8-STATE SHIFT
REGISTER
QS
2
QS
1
10
9
1
STR
8-BIT STORAGE
REGISTER
15
OE
3-STATE OUTPUTS
QP
0
QP
1
QP
2
QP
3
QP
4
Q5
1
QP
6
QP
7
4
5
6
7
14
13
12
11
SV01614
LOGIC DIAGRAM
STAGE 0
D
D
Q
FF0
CP
CP
CP
D
STAGES 1 TO 6
Q
STAGE 7
D
Q
D
CP
latch
D
Q
D
Q
Q
Q
7’
QS
2
FF7
CP
latch
CP
STR
OE
latch
CP
QP
0
QP
1
QP
2
QP
3
QP
4
QP
5
QP
6
QP
7
SV01615
1998 Jun 23
3
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
FUNCTION TABLE
INPUTS
CP
↑
↓
↑
↑
↑
↓
OE
L
L
H
H
H
H
STR
X
X
L
H
H
H
D
X
X
X
L
H
H
PARALLEL OUTPUT
QP
0
Z
Z
NC
L
H
NC
QP
n
Z
Z
NC
QP
n–1
QP
n–1
NC
SERIAL OUTPUTS
QS
1
Q’
6
NC
Q’
6
Q’
6
Q’
6
NC
QS
2
NC
QP
7
NC
NC
NC
QP
7
NOTES:
H = HIGH voltage level
L
= LOW voltage level
X = don’t care
Z
= high impedance OFF-state
NC = no change
↑
=
LOW-to–HIGH CP transition
↓
= HIGH-to-LOW CP transition
Q’
6
= the information in the 8
th
register stage is transferred to the
8
th
register stage and QS
n
clock edge.
TIMING DIAGRAM
CLOCK INPUT
CP
DATA INPUT
D
STROBE INPUT
STR
OUTPUT ENABLE INPUT
OE
INTERNAL Q’0 (FF0)
Z–state
OUTPUT
QP
0
INTERNAL Q’6 (FF6)
Z–state
OUTPUT
QP
6
QS
1
QS
2
SERIAL OUTPUT
SERIAL OUTPUT
SV01616
1998 Jun 23
4
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
ABSOLUTE MAXIMUM RATINGS
NO TAG, NO TAG
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
"I
IK
"I
OK
"I
O
"I
GND
,
"I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
– standard outputs
Storage temperature range
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +7.0
20
50
25
50
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
Input voltage
Output voltage
Operating ambient temperature range in free air
Input rise and fall times except for
Schmitt-trigger inputs
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
PARAMETER
DC supply voltage
CONDITIONS
See Note NO TAG
MIN
1.0
0
0
–40
–40
–
–
–
–
–
–
TYP
3.3
–
–
MAX
3.6
V
CC
V
CC
+85
+125
500
200
100
UNIT
V
V
V
°C
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
1998 Jun 23
5
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