Preliminary
WB1330
Dual Serial Input PLL with 2.5GHz and 600MHz Prescalers
Features
• Operating voltage 2.7V to 5.5V
• PLL1 operating frequency:
- 2.5GHz with prescaler ratios of 32/33 and 64/65
• PLL2 operating frequency:
- 600MHz with prescaler ratios of 8/9 and 16/17
• Lock detect feature
• Power-down mode I
CC
< 1µA typical at 3.0V
• 20-pin TSSOP (Thin Shrink Small Outline Package)
Figure 1
Pin Diagram
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
GND
F
O
/LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2
V
P
2
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
Applications
The IC WORKS WB1330 is a dual serial input PLL frequency
synthesizer designed to combine the RF and IF mixer fre-
quency sections of wireless communications systems. One
2.5GHz and one 600MHz prescaler, each with pulse swallow
capability are included. The device operates from 2.7V and
dissipates only 30mW. (See Figure 3 for an example applica-
tion diagram of the WB1330.)
Table 1
WB1330
Order Information: WB1330X-TR
Package
X = TSSOP
(0.173" Wide)
TR
Tape & Reel
Option
Part Number
Note:
Operating temperature range: –40°C to +85°C.
Figure 2
WB1330 Dual Hi-Lo PLL Block Diagram
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
V
P
1 (2)
F
IN
1 (5)
F
IN
1# (6)
Prescaler
32/33 or
64/65
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp1
Phase
Detector
Charge
Pump
D
O
PLL1 (3)
19-Bit
Latch
OSC_IN (8)
Pwr-dwn
PLL1
fr1
fr fp
Monitor
Output
Selector
15-Bit
Reference Counter
Latch
Selector
LE (13)
DATA (12)
CLOCK (11)
20-Bit Latch
20-Bit Latch
15-Bit
Reference Counter
19-Bit
Latch
Pwr-dwn
PLL2
F
O
/LD (10)
fr2
Cntrl 22-Bit
Shift
Reg.
Power
Control
F
IN
2 (16)
F
IN
2# (15)
Prescaler
8/9 or
16/17
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Phase
Detector
fp2
Charge
Pump
D
O
PLL2 (18)
GND (14)
GND (9)
GND (17)
V
P
2 (19)
August 1999
Revision 0.9.2
IC WORKS · 101 Nicholson Lane · San Jose, CA 95134-1359 · (408) 922-0202
Current information is available at www.icworks.com
Preliminary
WB1330
Pin Definitions
Pin Name
V
CC
1
V
P
1
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
GND
F
O
/LD
Pin
No.
1
2
3
4
5
6
7
8
9
10
Pin
Type
P
P
O
G
I
I
G
I
G
O
Pin Description
Power Supply Connection for PLL1 and PLL2:
When power is removed from both
the V
CC
1 and V
CC
2 pins, all latched data is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with
tuning voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is I
P
/2π. Sense polarity can
be reversed by setting the FC bit in software (via the Shift Register).
Analog and Digital Ground Connection:
This pin must be grounded.
Input to PLL1 Prescaler:
Maximum frequency 2.5GHz.
Complementary Input to PLL1 Prescaler:
A bypass capacitor should be placed as
closely as possible to this pin and must be connected directly to the ground plane.
Analog and Digital Ground Connection:
This pin must be grounded.
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS logic level sensitivity.
Reference Ground Connection:
This pin must be grounded.
Lock Detect Pin of PLL1 Section:
This output is high when the loop is locked. It is
multiplexed to the output of the programmable counters or reference dividers in the
test program mode.(Refer to Table 4 for configuration)
Data Clock Input:
One bit of data is loaded into the Shift Register on the rising edge
of this signal.
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored in the Shift Register
is latched into the reference counter and configuration controls, PLL1 or PLL2
depending on the state of the control bits.
Analog and Digital Ground Connection:
This pin must be grounded.
Complementary Input to PLL2 Prescaler:
A bypass capacitor should be placed as
closely as possible to this pin and must be connected directly to the ground plane.
Input to PLL2 Prescaler:
Maximum frequency 600MHz.
Analog and Digital Ground Connections:
This pin must be grounded.
PLL2 Charge Pump Output:
The phase detector gain is I
P
/2π. Sense polarity can
be reversed by setting the FC bit in software (via the Shift Register).
PLL2 Charge Pump Rail Voltage:
This voltage accommodates VCO circuits with
tuning voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When power is removed from
both the V
CC
1 and V
CC
2 pins, all latched data is lost.
CLOCK
DATA
LE
11
12
13
I
I
I
GND
F
IN
2#
F
IN
2
GND
D
O
PLL2
V
P
2
V
CC
2
14
15
16
17
18
19
20
G
I
I
G
O
P
P
Note:
Never have both PLLs programmed to the same frequency. They will lock to each other under these conditions. The
divide ratio can be calculated using the following equation:
fvco = {(P * B) + A} * fosc / R where (A < B)
fvco: Output frequency of the external VCO.
fosc: The crystal reference oscillator frequency.
A: Preset divide ratio of the 7-bit swallow counter (0 to 63) and the 4-bit swallow counter (0 to 15).
B: Preset ratio of the 11-bit programmable counter (3 to 2047).
P: Preset divide ratio of the dual modulus prescaler (32 or 64 and 8 or 16).
R: Preset ratio of the 15-bit programmable reference counter (3 to 32767).
The divide ratio N = (P * B) + A.
Dual Serial Input PLL with 2.5GHz and 600MHz Prescalers
Revision 0.9.2
Page 3
Preliminary
WB1330
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
rating only. Operation of the device at these or any other con-
Symbol
V
CC
or V
P
V
OUT
I
OUT
T
L
T
STG
Parameter
Power Supply Voltage
Output Voltage
Output Current
Lead Temperature
Storage Temperature
ditions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to + 6.5
–0.5 to V
CC
+0.5
±15
+260
–55 to +150
Unit
V
V
mA
°C
°C
Handling Precautions
Devices should be transported and stored in antistatic con-
tainers.
These devices are static sensitive. Ensure that equipment
and personnel contacting the devices are properly grounded.
Cover workbenches with grounded conductive mats.
Always turn off power before adding or removing devices
from system.
Protect leads with a conductive sheet when handling or trans-
porting PC boards with devices.
If devices are removed from the moisture protective bags for
more than 36 hours, they should be baked at 85°C in a mois-
ture free environment for 24 hours prior to assembly in less
than 24 hours.
Recommended Operating Conditions
Symbol
V
CC1
,
V
CC2
V
P
T
A
Parameter
Power Supply Voltage
Charge Pump Voltage
Operating Temperature
Rating
2.7 to 5.5
V
CC
to +5.5
–40 to +85
Unit
V
V
°C
Ambient air at 0 CFM flow
Test Condition
Page 4
Dual Serial Input PLL with 2.5GHz and 600MHz Prescalers
Revision 0.9.2
DSP and ARM Processors
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