Recommended connections to the PLRXPL-VE-SG4-38/PLRXPL-VI-SG4-38
transceiver are shown in Figure 2 below.
10K
Receiver (Tx Fault)
Open Collector
Driver (Tx Disable)
R1
*
50
Z = 100
*
PECL
Driver
(TX DATA)
SFP Host Connector
10K
1 VeeT
2 Tx Fault
10K
3 Tx Disable
4 MOD_DEF(2)
5 MOD_DEF(1)
10K
6 MOD_DEF(0)
7 Rate select
8 LOS
9 VeeR
VeeT 20
TD- 19
TD+ 18
VeeT 17
VccT 16
VccR 15
VeeR 14
RD+ 13
RD- 12
VeeR 11
C4
Open Collector
Bidirectional
{Mod_Def(2)}
R2
*
50
C3
0.1 F
L1
1 H
C2
L2
1 H
C5
10
u
F
0.1 F
C1
10 F
+3.3V
Vcc
Input
Open Collector
Bidirectional
{Mod_Def(1)}
Receiver
{Mod_Def(0)}
0.1uF
Receiver and
Transmitter
Rate Select
10 VeeR
10K
Receiver (LOS)
Z = 100
*
R3
50
*
PECL
Receiver
(RX DATA)
R4
*
50
Notes
Power supply filtering components should be placed as close to the V
cc
pins of the host connector as possible for optimal performance.
PECL driver and receiver will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are supported.
MOD_DEF(2) and MOD_DEF(1) should be bi-directional open collector connections in order to implement serial ID (MOD_DEF[0,1,1]) PLRXPL-VE-SG4-38 transceiver.
R1 and R2 may be included in the output of the PHY. Check application notes of the IC in use.
* Transmission lines should be 100
Ω
differential traces. It is recommended that the termination resistor for the PECL Receiver (R3 + R4) be placed beyond the input pins of the
PECL Receiver. Series Source Termination Resistors on the PECL Driver (R1+R2) should be placed as close to the driver output pins as possible
Figure 2
Recommended application schematic for the PLRXPL-VE-SG4-38/ PLRXPL-VI-SG4-38 transceiver
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