INTEGRATED CIRCUITS
74LVC27
Triple 3-input NOR gate
Product specification
Supersedes data of 1998 Apr 06
IC24 Data Handbook
1998 Apr 28
Philips
Semiconductors
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74LVC27
FEATURES
•
Wide supply voltage: 1.2 to 3.6 V
•
In accordance with JEDEC standard no. 8-1A.
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Output capability: standard
•
I
CC
category: SSI
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
nA, nB, nC to nY
Input capacitance
Power dissipation capacitance per gate
DESCRIPTION
The 74LVC27 is a high-performance, low-power, low-voltage Si-gate
CMOS device and superior to most advanced CMOS compatible
TTL families.
The 74LVC27 provides the 3-input NOR function.
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
Notes 1 and 2
TYPICAL
3.4
5.0
26
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC27 D
74LVC27 DB
74LVC27 PW
NORTH AMERICA
74LVC27 D
74LVC27 DB
74LVC27PW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
LOGIC SYMBOL (IEEE/IEC)
1
2
13
≥
1
12
1C
1Y
3C
3B
3A
3Y
3
4
5
≥
1
6
9
SV00446
≥
1
8
10
11
SV00448
1998 Apr 28
2
853-2056 19309
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74LVC27
PIN DESCRIPTION
PIN
NUMBER
1, 3, 9
2, 4, 10
13, 5, 11
7
12, 6, 8
14
SYMBOL
1A – 3A
1B – 3B
1C – 3C
GND
1Y – 3Y
V
CC
NAME AND FUNCTION
Data inputs
Data inputs
Data inputs
Ground (0 V)
Data outputs
Positive supply voltage
LOGIC DIAGRAM (ONE GATE)
A
B
Y
C
SV00449
LOGIC SYMBOL
1
2
13
3
4
5
9
10
11
1A
1B
1C
2A
1Y
12
FUNCTION TABLE
INPUTS
nA
L
X
2Y
OUTPUTS
nC
L
H
X
X
nY
H
L
L
L
nB
L
X
H
X
2B
2C
3A
3B
3C
6
X
H
3Y
8
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don’t care
SV00447
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
LIMITS
MIN
2.7
1.2
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
+85
20
10
UNIT
V
V
V
V
°C
ns/V
1998 Apr 28
3
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74LVC27
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t
0
Note 2
V
O
uV
CC
or V
O
t
0
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +5.5
"50
–0.5 to V
CC
+0.5
"50
"100
–60 to +150
500
500
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
O
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –12mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
CC
∆I
CC
Input leakage current
Quiescent supply current
Additional quiescent supply current per
input pin
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
"0.1
"0
1
0.1
5
GND
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*1.0
0.40
0.20
0.55
"5
10
500
µA
µA
µA
V
V
CC
V
V
CC
2.0
GND
V
0.8
TYP
1
MAX
V
UNIT
V
IL
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
1998 Apr 28
4
Philips Semiconductors
Product specification
Triple 3-input NOR gate
74LVC27
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF; R
L
= 500W; T
amb
= –40_C to +85_C
LIMITS
SYMBOL
t
PHL
/
t
PLH
PARAMETER
Propagation delay
nA, nB, nC to nY
WAVEFORM
MIN
Figure 1, 2
–
V
CC
= 3.3V
±0.3V
TYP
1
3.4
MAX
5.9
V
CC
= 2.7V
MIN
–
MAX
7.0
ns
UNIT
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
w
2.7 V
V
M
= 0.5
S
V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
VI
nA, nB, nC
INPUT
GND
t PHL
VOH
nY OUTPUT
VOL
VM
t PLH
VM
TEST CIRCUIT
V
CC
S
1
2 * V
CC
Open
GND
500Ω
V
I
PULSE
GENERATOR
R
T
D.U.T.
V
O
50pF
C
L
500Ω
SWITCH POSITION
TEST
S
1
Open
V
CC
< 2.7V
2.7–3.6V
V
I
V
CC
2.7V
SV00420
t
PLH/
t
PHL
Figure 1. Input (nA, nB, nC) to output (nY) propagation delays.
SV00903
Figure 2. Load circuitry for switching times.
1998 Apr 28
5
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