Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC573A
FEATURES
•
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•
Supply voltage range of 2.7V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
High impedance when V
CC
= 0V
•
Flow-through pin-out architecture
DESCRIPTION
The 74LVC573A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC573A is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for
bus-oriented applications. A latch enable (LE) input and an output
enable (OE) input are common to all internal latches.
The ’573A’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D
n
inputs enters the
latches. In this condition, the latches are transparent, i.e. a latch
output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present
at the D-inputs one setup time preceding the HIGH-to-LOW
transition of LE. When OE is LOW, the contents of the eight latches
are available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The ’573A’ is functionally identical to the ’373A’, but the ’373A’ has a
different pin arrangement.
QUICK REFERENCE DATA
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
D
n
to Q
n;
LE to Q
n
Input capacitance
Power dissipation capacitance per latch
Notes 1 and 2
CONDITIONS
C
L
= 50pF
V
CC
= 3.3V
TYPICAL
UNIT
ns
pF
pF
4.3
4.6
5.0
20
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
mW):
P
D
= C
PD
x V
CC2
x f
i
+
S
(C
L
x V
CC2
x f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
x V
CC2
x f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO)
20-Pin Plastic Shrink Small Outline (SSOP) Type II
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE
NORTH AMERICA
74LVC573A D
74LVC573A DB
74LVC573A PW
NORTH AMERICA
74LVC573A D
74LVC573A DB
7LVC573APW DH
PKG. DWG. #
SOT163-1
SOT339-1
SOT360-1
1998 Jul 29
2
853-1862 19804
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
74LVC573A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
DC supply voltage (for max. speed performance)
V
CC
V
I
V
O
T
amb
t
r
, t
f
DC supply voltage (for low-voltage applications)
DC Input voltage range
DC output voltage range; output HIGH or LOW
state
DC output voltage range; output 3-State
Operating ambient temperature range in free-air
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
MIN
2.7
1.2
0
0
0
–40
0
0
MAX
3.6
V
3.6
5.5
V
CC
5.5
+85
20
10
°C
ns/V
V
V
UNIT
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage; output HIGH or LOW state
DC output voltage; output 3-State
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t0
Note 2
V
O
uV
CC
or V
O
t
0
Note 2
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +6.5
"50
–0.5 to V
CC
+0.5
–0.5 to 6.5
"50
"100
–65 to +150
500
500
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
FPGA/CPLD
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