INTEGRATED CIRCUITS
74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
IC24 Data Handbook
1998 Jun 17
Philips
Semiconductors
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
FEATURES
DESCRIPTION
74LVC74A
•
Wide supply voltage range of 1.2 V to 3.6 V
•
In accordance with JEDEC standard no. 8-1A.
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Output drive capability 50
W
transmission lines @ 85°C
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.
The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
Notes 1 and 2
CONDITIONS
TYPICAL
3.6
3.5
3.5
250
5.0
30
UNIT
t
PHL/
t
PLH
f
max
C
I
C
PD
C
L
= 50 pF;
V
CC
= 3.3 V
ns
MHz
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) + (V
O2
/R
L
)
×
duty factor LOW, where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC74A D
74LVC74A DB
74LVC74A PW
NORTH AMERICA
74LVC74A D
74LVC74A DB
74LVC74APW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1R
D
1D
1CP
1S
D
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2R
D
2D
2CP
2S
D
2Q
2Q
LOGIC SYMBOL (IEEE/IEC)
4
3
2
1
S
C1
1D
R
6
5
10
11
12
S
C2
2D
R
9
SV00491
13
8
SV00332
1998 Jun 17
2
853-2070 19589
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74LVC74A
PIN DESCRIPTION
PIN
NUMBER
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL
1R
D
, 2R
D
1D, 2D
1CP, 2CP
1S
D
, 2S
D
1Q, 2Q
1Q, 2Q
GND
V
CC
NAME AND FUNCTION
Asynchronous reset-direct input
(active LOW)
Data inputs
Clock input (LOW-to-HIGH, edge
triggered)
Asynchronous set-direct input (active
LOW)
True flip-flop outputs
Complement flip-flop outputs
Ground (0 V)
Positive supply voltage
FUNCTION TABLE
INPUTS
S
D
L
H
L
R
D
H
L
L
INPUTS
S
D
H
H
R
D
H
H
CP
°
°
D
L
H
CP
X
X
X
D
X
X
X
OUTPUTS
Q
H
L
H
Q
L
H
H
OUTPUTS
Q
n+1
L
H
Q
n+1
H
L
LOGIC SYMBOL
4 10
1S
D
2S
D
S
D
2 1D
1Q
D
Q
12 2D
2Q
3 1CP
FF
CP
11 2CP
1Q
Q
2Q
R
D
1R
D
2R
D
1 13
5
9
5
9
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = don“t care
°
= LOW-to-HIGH CP transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
FUNCTIONAL DIAGRAM
4
2
3
1S D
1D
1CP
D
SD
Q
1Q
5
CP FF1
Q
RD
1Q
6
SV00492
1 1R D
10
12
11
2S D
2D
2CP
D
SD
Q
2Q
9
CP FF2
Q
RD
2Q
8
13 2R
D
SV00494
1998 Jun 17
3
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74LVC74A
LOGIC DIAGRAM (ONE FLIP-FLOP)
Q
C
C
C
C
D
C
RD
SD
CP
C
C
C
C
Q
C
SV00495
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.2 to 2.7V
V
CC
= 2.7 to 3.6V
CONDITIONS
LIMITS
MIN
2.7
1.2
0
0
–40
0
0
MAX
3.6
3.6
5.5
V
CC
+85
20
10
UNIT
V
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
t
0
Note 2
V
O
uV
CC
or V
O
t
0
Note 2
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +6.5
–50
–0.5 to +5.5
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
500
500
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 17
4
Philips Semiconductors
Product Specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74LVC74A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
LOW level Input voltage
V
CC
= 1.2V
V
CC
= 2.7 to 3.6V
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
O
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –18mA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100µA
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
I
I
I
CC
∆I
CC
Input leakage current
Quiescent supply current
Additional quiescent supply current per
input pin
V
CC
= 3 6V; V
I
= 5 5V or GND
3.6V;
5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
"0.1
"0
1
0.1
5
GND
V
CC
*0.5
V
CC
*0.2
V
CC
*0.6
V
CC
*1.0
0.40
0.20
0.55
"5
10
500
µA
µA
µA
V
V
CC
V
V
CC
2.0
GND
V
0.8
TYP1
MAX
V
UNIT
V
IL
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
v
2.5 ns; C
L
= 50 pF; R
L
= 500W; T
amb
= –40_C to +85_C
LIMITS
SYMBOL
PARAMETER
Propagation delay
nCP to nQ, nQ
t
PHL
/
t
PLH
Propagation delay
nS
D
to nQ, nQ
Propagation delay
nR
D
to nQ, nQ
t
W
t
rem
t
su
t
h
f
max
Clock pulse width HIGH or LOW
Set or reset pulse width LOW
Removal time set or reset
Set-up time nD to nCP
Hold time nD to nCP
Maximum clock pulse frequency
WAVEFORM
V
CC
= 3.3V
±0.3V
MIN
Figures 1, 3
Figures 2, 3
Figures 2, 3
Figure 1
Figure 2
Figure 2
Figure 1
Figure 1
Figure 1
1.5
1.5
1.5
3.3
3.3
1
2.0
1
150
TYP
1
3.6
3.5
3.5
1.3
1.7
–3
0.8
–0.7
250
MAX
5.2
5.4
5.4
–
–
–
–
–
–
V
CC
= 2.7V
MIN
–
–
–
–
–
–
–
–
–
MAX
6.0
6.4
6.4
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
MHz
UNIT
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25°C.
1998 Jun 17
5
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