AS29LV400B-70SC datasheet, PDF

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AS29LV400B-70SC: DescriptionFlash, 256KX16, 70ns, PDSO44, PLASTIC, MO-175AA, SO-44; Categorystorage storage; File Size240KB，26 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS29LV400B-70SC Overview

Flash, 256KX16, 70ns, PDSO44, PLASTIC, MO-175AA, SO-44

AS29LV400B-70SC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	PLASTIC, MO-175AA, SO-44
Contacts	44
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	70 ns
Spare memory width	8
JESD-30 code	R-PDSO-G44
length	28.2 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	16
Humidity sensitivity level	1
Number of functions	1
Number of terminals	44
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	3.1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	12.6 mm
Base Number Matches	1

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• Organization: 512Kx8/256Kx16

• Sector architecture

- One 16K; two 8K; one 32K; and seven 64K byte sectors

- One 8K; two 4K; one 16K; and seven 32K word sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/write operations

• Sector protection

• High speed 70/80/90/120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/verifies data at specified address

• Automated on-chip erase algorithm

- Automatically preprograms/erases chip or specified

sectors

• Hardware

RE S E T

- Resets internal state machine to read mode

• Low power consumption

- 200 nA typical automatic sleep mode current

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO; availability TBD

• Detection of program/erase cycle completion

- DQ7

DATA

polling

- DQ6 toggle bit

- DQ2 toggle bit

- RY/

output

• Erase suspend/resume

- Supports reading data from or programming data

to a sector not being erased

• Low V

write lock-out below 1.5V

• 10 year data retention at 150C

• 100,000 write/erase cycle endurance

DQ0–DQ15

/RJLF EORFN GLDJUDP

RY/BY

Sector protect/

erase voltage

switches

Erase voltage

generator

RESET

BYTE

Command

Program/erase

control

Input/output

buffers

Program voltage

generator

Chip enable

Output enable

Logic

STB

Data latch

A-1

detector

Timer

Address latch

STB

Y decoder

Y gating

X decoder

Cell matrix

A0–A17

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Maximum access time

Maximum chip enable access time

Maximum output enable access time

29LV400-70

29LV400-80

29LV400-90

29LV400-120

120

Unit

9/26/01; V.0.9.9.2

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The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible

Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k

byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears

on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP and 44-pin SO. This device is designed to be

programmed and erased with a single 3.0V V

supply. The device can also be reprogrammed in standard EPROM programmers.

The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To

eliminate bus contention the device has separate chip enable

(C E )

, write enable

(WE )

, and output enable

(O E )

controls. Word

mode (×16 output) is selected by

B YT E

= high. Byte mode (×8 output) is selected by

BY TE

= low.

The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor

write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and

programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations.

Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip

programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase

command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already

programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper

cell margins.

Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector.

Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other

sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the

Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend,

which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip

Erase command will automatically erase all unprotected sectors.

When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is

programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change

bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no

effect on other sectors.

The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and

regulated voltages are provided for the Program and Erase operations. A low V

detector automatically inhibits write operations

during power transtitions. The

RY/BY

pin,

DATA

polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the

program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are

completed. DQ2 indicates which sectors are being erased.

The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control

register architecture permits alteration of memory contents only when successful completion of specific command sequences has

occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if V

is less than V

LKO

(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on

O E , CE , or WE

. To initiate Write

commands,

and

must be a logical zero and

O E

a logical 1.

When the device’s hardware

R E S E T

pin is driven low, any Program/Erase operation in progress is terminated and the internal

state machine is reset to Read mode. If the

RE S E T

pin is tied to the system reset circuitry and a system reset occurs during an

automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require

rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are

programmed one at a time using the EPROM programming mechanism of hot electron injection.

9/26/01; V.0.9.9.2

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